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    Methods of manufacturing memory units, and methods of manufacturing semiconductor devices
    11.
    发明授权
    Methods of manufacturing memory units, and methods of manufacturing semiconductor devices 失效
    制造存储器单元的方法以及制造半导体器件的方法

    公开(公告)号：US07790610B2

    公开(公告)日：2010-09-07

    申请号：US12339577

    申请日：2008-12-19

    Applicant: Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

    Inventor： Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

    IPC: H01L21/44

    CPC classification number: H01L27/11507 ,  B82Y10/00 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/24

    Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.

    Abstract translation: 提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。 第一电极层被部分地去除以在第一纳米线下方形成第一电极。 填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。 在第一纳米线和第一绝缘层上形成第二电极层。 多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。 使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。 还提供了相关的存储器单元，制造半导体器件和半导体器件的方法。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    13.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20090209071A1

    公开(公告)日：2009-08-20

    申请号：US12388012

    申请日：2009-02-18

    Applicant: Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

    Inventor： Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

    IPC: H01L21/8238

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  G11C2213/16 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L27/1052 ,  H01L27/24 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/775

    Abstract: First nanowires and second nanowires are alternately disposed and spaced apart on a first substrate in a second direction that is parallel to an adjacent major surface of the first substrate. Each of the first and second nanowires extends in a first direction that is perpendicular to the second direction, and the first and second nanowires are doped with first and second conductive types, respectively. A plurality of gate lines are formed that are at least partially disposed within the first substrate, that are spaced apart in a third direction, that extend in a fourth direction that is perpendicular to the third direction, and that partially enclose the first and second nanowires

    Abstract translation: 第一纳米线和第二纳米线在平行于第一基板的相邻主表面的第二方向上交替地设置和间隔在第一基板上。 第一和第二纳米线中的每一个在垂直于第二方向的第一方向上延伸，并且第一和第二纳米线分别掺杂有第一和第二导电类型。 形成多个栅极线，其至少部分地设置在第一基板内，在第三方向上间隔开，沿与第三方向垂直的第四方向延伸，并且部分地包围第一和第二纳米线

    Methods of Manufacturing Memory Units, and Methods of Manufacturing Semiconductor Devices
    14.
    发明申请
    Methods of Manufacturing Memory Units, and Methods of Manufacturing Semiconductor Devices 失效
    制造存储器单元的方法和制造半导体器件的方法

    公开(公告)号：US20090162998A1

    公开(公告)日：2009-06-25

    申请号：US12339577

    申请日：2008-12-19

    Applicant: Moon-Sook Lee ,  Byeong Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

    Inventor： Moon-Sook Lee ,  Byeong Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

    IPC: H01L21/768 ,  H01L21/20

    CPC classification number: H01L27/11507 ,  B82Y10/00 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/24

    Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.

    Abstract translation: 提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。 第一电极层被部分地去除以在第一纳米线下方形成第一电极。 填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。 在第一纳米线和第一绝缘层上形成第二电极层。 多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。 使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。 还提供了相关的存储单元，制造半导体器件和半导体器件的方法。

    Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same
    15.
    发明授权
    Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same 有权
    使用二元金属氧化物层作为数据存储材料层的交叉点非易失性存储器件及其制造方法

    公开(公告)号：US07535035B2

    公开(公告)日：2009-05-19

    申请号：US11241604

    申请日：2005-09-30

    Applicant: In-Gyu Baek ,  Moon-Sook Lee

    Inventor： In-Gyu Baek ,  Moon-Sook Lee

    IPC: H01L29/73 ,  H01L21/82

    CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

    Abstract: A cross-point nonvolatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines disposed in a substrate. Spaced apart upper electrodes cross over the doped lines such that cross points are formed where the upper electrodes overlap the doped lines. Lower electrodes are disposed at the cross points between the doped lines and the upper electrodes. A binary metal oxide layer is provided between the upper electrodes and the lower electrodes and provided as a data storage material layer. Doped regions are provided between the lower electrodes and the doped lines and form diodes together with the doped lines. The doped regions have an opposite polarity to the doped lines.

    Abstract translation: 使用二元金属氧化物层作为数据存储材料层的交叉点非易失性存储器件包括设置在衬底中的间隔开的掺杂线。 间隔开的上电极在掺杂线上交叉，使得形成交叉点，其中上电极与掺杂线重叠。 下电极设置在掺杂线和上电极之间的交叉点处。 在上部电极和下部电极之间设置二元金属氧化物层，作为数据存储材料层。 掺杂区域设置在下电极和掺杂线之间，并与掺杂线一起形成二极管。 掺杂区域具有与掺杂线相反的极性。

    Method and apparatus for forming a ferroelectric layer
    19.
    发明申请
    Method and apparatus for forming a ferroelectric layer 审中-公开
    形成铁电层的方法和装置

    公开(公告)号：US20050019960A1

    公开(公告)日：2005-01-27

    申请号：US10889035

    申请日：2004-07-13

    Applicant: Moon-Sook Lee ,  Byoung-Jae Bae

    Inventor： Moon-Sook Lee ,  Byoung-Jae Bae

    IPC: H01L21/205 ,  C23C16/44 ,  C23C16/452 ,  C23C16/455 ,  H01L27/105 ,  H01L21/00

    CPC classification number: C23C16/45565 ,  C23C16/4411 ,  C23C16/452 ,  C23C16/45514

    Abstract: Methods and apparatus for depositing a layer including providing at least one precursor vapor to a process chamber, providing a gas to the process chamber, separate from the at least one precursor vapor, and forming a compound layer from the at least one precursor vapor and the gas on a wafer in the process chamber. The deposition may be a chemical vapor deposition (CVD) deposition method, a metal organic chemical vapor deposition (MOCVD) deposition method, an atomic layer deposition (ALD) deposition method, or other similar deposition method. The compound layer may be at least one of an oxide, nitride, carbide, or other similar layer.

    Abstract translation: 用于沉积层的方法和装置，包括向处理室提供至少一种前体蒸气，向处理室提供气体，与至少一种前体蒸气分离，以及从至少一种前体蒸气形成化合物层， 气体在处理室中的晶片上。 沉积可以是化学气相沉积（CVD）沉积方法，金属有机化学气相沉积（MOCVD）沉积法，原子层沉积（ALD）沉积法或其它类似的沉积方法。 化合物层可以是氧化物，氮化物，碳化物或其它类似层中的至少一种。

    Thin film transistors and methods of manufacturing thin film transistors
    20.
    发明授权
    Thin film transistors and methods of manufacturing thin film transistors 有权
    薄膜晶体管和制造薄膜晶体管的方法

    公开(公告)号：US08586427B2

    公开(公告)日：2013-11-19

    申请号：US13204785

    申请日：2011-08-08

    Applicant: Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

    Inventor： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

    IPC: H01L21/8234 ,  H01L29/786

    CPC classification number: H01L29/41733 ,  H01L27/1292 ,  H01L29/42384

    Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

    Abstract translation: 薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。 源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。 源极线可以部分地与栅电极重叠，使得与栅极重叠的源极线的两侧可以完全位于栅电极的两侧之间。 漏极线可以与沟道层接触并且可以与源极线隔开通道长度。 漏极线可以具有与源极线对称的结构。 可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

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