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    Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
    11.
    发明授权
    Method of forming different silicide portions on different silicon-containing regions in a semiconductor device 有权
    在半导体器件中在不同含硅区域上形成不同硅化物部分的方法

    公开(公告)号：US07226859B2

    公开(公告)日：2007-06-05

    申请号：US10282720

    申请日：2002-10-29

    Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC: H01L29/40

    CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933

    Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

    Abstract translation: 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着提高单个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

    Field effect transistor with reduced gate delay and method of fabricating the same
    12.
    发明授权
    Field effect transistor with reduced gate delay and method of fabricating the same 有权
    具有减小的栅极延迟的场效应晶体管及其制造方法

    公开(公告)号：US06798028B2

    公开(公告)日：2004-09-28

    申请号：US09847622

    申请日：2001-05-02

    Applicant: Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    Inventor： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    IPC: H01L2976

    CPC classification number: H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

    Abstract: A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

    Abstract translation: 形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。 与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是 缩小到100nm以上的尺寸。 此外，公开了一种用于形成上述场效应晶体管的方法。

    Enhancing transistor characteristics by a late deep implantation in combination with a diffusion-free anneal process
    13.
    发明授权
    Enhancing transistor characteristics by a late deep implantation in combination with a diffusion-free anneal process 有权
    通过与无扩散退火工艺结合的深深植入来增强晶体管特性

    公开(公告)号：US08288256B2

    公开(公告)日：2012-10-16

    申请号：US12023743

    申请日：2008-01-31

    Applicant: Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

    Inventor： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

    IPC: H01L21/425

    CPC classification number: H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

    Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

    Abstract translation: 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。 以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

    In situ monitoring of metal contamination during microstructure processing
    14.
    发明授权
    In situ monitoring of metal contamination during microstructure processing 有权
    微观处理过程中金属污染的原位监测

    公开(公告)号：US08158065B2

    公开(公告)日：2012-04-17

    申请号：US12507986

    申请日：2009-07-23

    Applicant: Martin Trentzsch ,  Stephan Kronholz ,  Rolf Stephan

    Inventor： Martin Trentzsch ,  Stephan Kronholz ,  Rolf Stephan

    IPC: G01N35/00 ,  G01R31/26 ,  H01L21/66 ,  G01N29/02

    CPC classification number: G01N27/221 ,  G01N27/226

    Abstract: By providing a tool internal sensor device in a process tool in a semiconductor facility, metal contamination may be monitored in situ, thereby avoiding or at least significantly reducing the requirement for sophisticated sample preparation techniques, such as vapor phase decomposition tests in combination with subsequent analysis procedures. Thus, a full time inspection of process tools may be accomplished.

    Abstract translation: 通过在半导体设备中的工艺工具中提供工具内部传感器装置，可以原位监测金属污染，从而避免或至少显着地降低复杂的样品制备技术的需要，例如与后续分析相结合的气相分解测试 程序。 因此，可以完成对过程工具的全面检查。

    Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure
    15.
    发明授权
    Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure 有权
    形成半导体结构的方法，包括形成至少一个侧壁间隔结构

    公开(公告)号：US08003460B2

    公开(公告)日：2011-08-23

    申请号：US12028895

    申请日：2008-02-11

    Applicant: Frank Wirbeleit ,  Rolf Stephan ,  Peter Javorka

    Inventor： Frank Wirbeleit ,  Rolf Stephan ,  Peter Javorka

    IPC: H01L21/8238 ,  H01L21/336

    CPC classification number: H01L21/823864 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

    Abstract: According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process.

    Abstract translation: 根据说明性示例，形成半导体结构的方法包括提供包括第一特征和第二特征的半导体衬底。 在第一特征和第二特征上形成材料层。 在第一特征上形成掩模。 执行适于从材料层的一部分形成邻近第二特征的侧壁间隔结构的至少一个蚀刻工艺。 所述掩模保护所述第一特征上的所述材料层的一部分不受所述至少一个蚀刻工艺的影响。 进行离子注入工艺。 在离子注入过程中，掩模保留在第一个特征之上。

    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same
    17.
    发明授权
    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same 有权
    包括具有应力沟道区域的场效应晶体管的半导体结构及其形成方法

    公开(公告)号：US07608499B2

    公开(公告)日：2009-10-27

    申请号：US11685847

    申请日：2007-03-14

    Applicant: Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    Inventor： Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material layer is deposited over the first transistor element and the second transistor element. The stressed material layer is processed to form from the stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element. A pair of cavities is formed adjacent the gate electrode of the second transistor element. A pair of stress-creating elements is formed in the cavities and the hard mask is at least partially removed.

    Abstract translation: 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件和第二晶体管元件中的每一个包括栅电极。 在第一晶体管元件和第二晶体管元件上沉积应力材料层。 被施加的材料层被加工成从与第二晶体管元件的栅电极相邻的应力材料层侧壁间隔和覆盖第一晶体管元件的硬掩模形成。 在第二晶体管元件的栅电极附近形成一对空腔。 在空腔中形成一对应力产生元件，并且至少部分地去除硬掩模。

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