中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.022 seconds)

    Cross point memory array with memory plugs exhibiting a characteristic hysteresis
    11.
    发明授权
    Cross point memory array with memory plugs exhibiting a characteristic hysteresis 有权
    具有显示特征滞后的存储插头的交叉点存储器阵列

    公开(公告)号：US06850429B2

    公开(公告)日：2005-02-01

    申请号：US10330900

    申请日：2002-12-26

    Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Edmond R. Ward ,  Christophe J. Chevallier

    Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Edmond R. Ward ,  Christophe J. Chevallier

    IPC: G11C11/56 ,  G11C13/00 ,  G11C11/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/77

    Abstract: Providing a cross point, memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.

    Abstract translation: 提供交叉点，具有显示特征滞后的存储插件的存储器阵列。 存储插头表现出滞后现象，在低电阻状态下，第一写入阈值电压是高于其上施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，低于该电压脉冲将改变电阻 内存插头。 类似地，在高电阻状态下，第二写入阈值电压是低于施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且高于该电压脉冲将改变存储器插头的电阻。 施加到存储器插头的读取电压通常高于第一写入阈值电压并低于第二写入阈值电压。

    Method and apparatus for multiple byte or page mode programming of a flash memory array
    12.
    发明授权
    Method and apparatus for multiple byte or page mode programming of a flash memory array 有权
    用于闪存阵列的多字节或页面模式编程的方法和装置

    公开(公告)号：US06731544B2

    公开(公告)日：2004-05-04

    申请号：US10039518

    申请日：2001-11-08

    Applicant: Kyung Joon Han ,  Dung Tran ,  Steven W. Longcor ,  Steve K. Hsia

    Inventor： Kyung Joon Han ,  Dung Tran ,  Steven W. Longcor ,  Steve K. Hsia

    IPC: G11C1604

    CPC classification number: G11C16/16 ,  G11C16/10 ,  G11C16/3418

    Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

    Abstract translation: 存储器阵列包含使用Fowler-Nordheim（“FN”）在通道区域进行隧道扫描的存储单元，并使用通道热电子注入（“CHE”）或通道引发的二次电子注入（“CISEI”）进行编程， 。 为了在编程操作和读取操作期间减少未选择存储单元的浮动栅极电位的干扰，未选择的字线被带到负电位而不是地电位。 为了减少FN擦除操作期间未选择的存储单元的浮动栅极电势的干扰，未选择的字线被带到正电位而不是地电位。

    Memory Device Using Ion Implant Isolated Conductive Metal Oxide
    15.
    发明申请
    Memory Device Using Ion Implant Isolated Conductive Metal Oxide 有权
    使用离子注入隔离导电金属氧化物的存储器件

    公开(公告)号：US20110315948A1

    公开(公告)日：2011-12-29

    申请号：US13215895

    申请日：2011-08-23

    Applicant: DARRELL RINERSON ,  JONATHAN BORNSTEIN ,  DAVID HANSEN ,  ROBIN CHEUNG ,  STEVEN W. LONGCOR ,  RENE MEYER ,  LAWRENCE SCHLOSS

    Inventor： DARRELL RINERSON ,  JONATHAN BORNSTEIN ,  DAVID HANSEN ,  ROBIN CHEUNG ,  STEVEN W. LONGCOR ,  RENE MEYER ,  LAWRENCE SCHLOSS

    IPC: H01L45/00 ,  B82Y99/00

    CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

    Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

    Method of making a planar electrode
    16.
    发明申请
    Method of making a planar electrode 审中-公开
    制作平面电极的方法

    公开(公告)号：US20110204019A1

    公开(公告)日：2011-08-25

    申请号：US12927552

    申请日：2010-11-15

    Applicant: Jonathan Bornstein ,  David Hansen ,  Steven W. Longcor

    Inventor： Jonathan Bornstein ,  David Hansen ,  Steven W. Longcor

    IPC: H05K3/00

    Abstract: Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.

    Abstract translation: 公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。 低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。 随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。 所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。 可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

    Method of making a planar electrode
    17.
    发明授权
    Method of making a planar electrode 失效
    制作平面电极的方法

    公开(公告)号：US07832090B1

    公开(公告)日：2010-11-16

    申请号：US12660424

    申请日：2010-02-25

    Applicant: Jonathan Bornstein ,  David Hansen ,  Steven W. Longcor

    Inventor： Jonathan Bornstein ,  David Hansen ,  Steven W. Longcor

    IPC: H01R43/00

    CPC classification number: H01L27/24 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76849 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.

    Abstract translation: 公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。 低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。 随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。 所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。 可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

    Enhanced functionality in a two-terminal memory array
    20.
    发明授权
    Enhanced functionality in a two-terminal memory array 有权
    两端存储器阵列中增强的功能

    公开(公告)号：US07330370B2

    公开(公告)日：2008-02-12

    申请号：US11021600

    申请日：2004-12-23

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Steven W. Longcor ,  Edmond Ward ,  Robert Norman

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Steven W. Longcor ,  Edmond Ward ,  Robert Norman

    IPC: G11C11/00

    CPC classification number: G11C11/16

    Abstract: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.

    Abstract translation: 介绍了增强功能的内存阵列。 阵列中的每个单元包括一对存储元件电极。 一对存储元件电极上的读取电流表示存储的信息，并且跨该对存储元件电极的不同写入电压电平被用于存储非易失性信息。 该阵列具有至少一个增强功能部分，其执行从由参考，纠错，设备特定存储，缺陷映射表和冗余组成的组中选择的操作。

Patent Agency Ranking