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公开(公告)号：US20220155519A1
公开(公告)日：2022-05-19
申请号：US17649520
申请日：2022-01-31
Inventor： Frédéric Boeuf , Luca Maggi
Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
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公开(公告)号：US10852451B2
公开(公告)日：2020-12-01
申请号：US16197673
申请日：2018-11-21
Applicant: STMicroelectronics S.r.I.
Inventor： Daniele Mangano , Riccardo Condorelli
Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal determined by the analog peak detector.
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公开(公告)号：US20200230648A1
公开(公告)日：2020-07-23
申请号：US16747197
申请日：2020-01-20
Applicant: STMicroelectronics S.r.I.
Inventor： Andrea Barbieri , Aldo Vidoni
Abstract: A negative impedance circuit includes: a differential circuit stage; a positive feedback path from an output of the differential circuit stage to a first input of the differential circuit stage; and a negative feedback path from the output of the differential circuit stage to a second input of the differential circuit stage. The negative feedback path includes a first transistor, and a unitary gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unitary gain path coupled to ground via a reference impedance. The positive feedback path includes a second transistor. The first and second transistors are coupled in a current mirror arrangement and have respective control electrodes configured to be driven by the output of the differential circuit stage, where the negative impedance circuit causes a negative impedance at the first input of the differential circuit stage.
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14.发明申请公开(公告)号：US20190213000A1
公开(公告)日：2019-07-11
申请号：US16225557
申请日：2018-12-19
Applicant: STMicroelectronics S.r.I.
Inventor： Fabio Enrico Carlo Disegni
Abstract: A method for management of a differential memory includes storing first logic data associated with a first informative content in an auxiliary memory module of the differential memory; storing third logic data associated with a second informative content in a second submodule of a main memory module by overwriting second logic data associated with the first informative content while maintaining the first logic data contained in a first submodule of the main memory module unaltered; when the third logic data is being stored, reading the first logic data from the auxiliary memory module in a single-ended mode in response to a request for reading the first informative content; otherwise, reading the first logic data from the first submodule; and reading the third logic data in single-ended mode.
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公开(公告)号：US20180150093A1
公开(公告)日：2018-05-31
申请号：US15637225
申请日：2017-06-29
Applicant: STMicroelectronics S.r.I.
Inventor： Vanni Poletto , Biagio Provinzano
IPC: G05F1/575 , H03F3/45 , H03K19/003
CPC classification number: G05F1/575 , H03F3/45475 , H03F3/45511 , H03F3/505 , H03K17/04206 , H03K17/166 , H03K17/687 , H03K19/00361
Abstract: A (pre) driver circuit includes first and second output terminals configured to be coupled to a power transistor. A differential stage has non-inverting and inverting inputs for receiving an input voltage. The input voltage is replicated as an output voltage across the first and second output terminals as a drive signal for the power transistor. The differential stage includes a differential transconductance amplifier in a voltage follower arrangement configured to provide continuous regulation of a voltage at the first output terminal with respect to the second output terminal.
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Patent Agency Ranking
公开(公告)号：US09613432B2
公开(公告)日：2017-04-04
申请号：US14607570
申请日：2015-01-28
Applicant: STMicroelectronics S.r.I.
Inventor： Antonio Vincenzo Buemi
CPC classification number: G06T7/90 , G06K9/4652 , G06T2207/10024 , G06T2207/30232 , G08B17/125
Abstract: A digital image having a plurality of pixels is analyzed to detect a fire condition. A first color parameter is determined from image color values of pixels of the image. A plurality of fuzzy membership functions correlated to image colors are defined, the plurality of fuzzy membership functions including a first fuzzy color membership function having a trend defined by said first color parameter. A fuzzy inference procedure is applied to pixels of the image to determine whether a fire condition is indicated by the digital image.
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公开(公告)号：US20170085192A1
公开(公告)日：2017-03-23
申请号：US14856686
申请日：2015-09-17
Applicant: STMICROELECTRONICS S.r.I.
Inventor： Andrea AGNES , Christian BEIA
CPC classification number: H02M7/06 , G05F3/24 , G06F1/266 , H02M3/07 , H02M7/217 , H04L12/10 , H04L12/40045
Abstract: An electronic device includes a rectifier bridge that includes an input configured to be coupled to power over Ethernet (PoE) power sourcing equipment (PSE), and an output. A transistor is configured to selectively couple the output with a load. The electronic device includes a maintain power signature (MPS) device, and a control circuit. The control circuit is to maintain the transistor on when a load current is above a threshold, source current from the rectifier bridge to the MPS device when the load current is below the threshold, and switch the transistor to a diode configuration when the load current is below the threshold.
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公开(公告)号：US09240752B2
公开(公告)日：2016-01-19
申请号：US14216037
申请日：2014-03-17
Applicant: STMicroelectronics S.r.I.
Inventor： Egidio Ragonese , Vincenzo Fiore , Nunzio Spina , Giuseppe Palmisano
CPC classification number: H03B5/1212 , H03B1/02 , H03B5/02 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03B27/00 , H03B2200/0074 , H03B2200/0076 , H03B2200/0078
Abstract: An oscillator circuit includes first and second oscillators arranged in a series configuration between a supply voltage node and a reference voltage node. The first and second oscillators are configured to receive a synchronizing signal for controlling synchronization in frequency and phase. An electromagnetic network provided to couple the first and the second oscillators includes a transformer with a primary circuit and a secondary circuit. The primary circuit includes a first portion coupled to the first oscillator and second portion coupled to the second oscillator. The first and second portions are connected by a circuit element for reuse of current between the first and second oscillators. The oscillator circuit is fabricated as an integrated circuit device wherein the electromagnetic network is formed in metallization layers of the device. The secondary circuit generates an output power combining power provided from the first and second portions of the primary circuit.
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公开(公告)号：US20160011235A1
公开(公告)日：2016-01-14
申请号：US14751254
申请日：2015-06-26
Applicant: STMICROELECTRONICS S.r.I.
Inventor： Riccardo CONDORELLI , Daniele MANGANO
Abstract: A method of interfacing an LC sensor with a control unit is described. The control unit may include first and second contacts, and the LC sensor may be connected between the first and second contacts. The method may include starting the oscillation of the LC sensor, and monitoring the voltage at the second contact, in which the voltage at the second contact corresponds to the sum of the voltage at the first contact and the voltage at the LC sensor. The voltage at the first contact may be varied such that the voltage at the second contact does not exceed an upper voltage threshold and does not fall below a lower voltage threshold.
Abstract translation: 描述了将LC传感器与控制单元接口的方法。 控制单元可以包括第一和第二触点，并且LC传感器可以连接在第一和第二触点之间。 该方法可以包括启动LC传感器的振荡，以及监测第二接触处的电压，其中第二接触处的电压对应于第一接触处的电压和LC传感器的电压之和。 可以改变第一接触处的电压，使得第二接触处的电压不超过上限电压阈值，并且不低于低电压阈值。
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20.发明授权公开(公告)号：US09233834B2
公开(公告)日：2016-01-12
申请号：US14316504
申请日：2014-06-26
Applicant: STMicroelectronics S.r.I.
Inventor： Dino Faralli , Paolo Ferrari , Laura Maria Castoldi
CPC classification number: B81B3/0021 , B81B7/0016 , B81B7/0058 , B81B2201/0264 , B81B2203/0127 , B81B2207/115 , B81C1/00158 , B81C3/00 , B81C2203/0118 , H01L2224/48091 , H01L2224/48145 , H01L2924/00014 , H01L2924/00012
Abstract: A MEMS device wherein a die of semiconductor material has a first face and a second face. A diaphragm is formed in or on the die and faces the first surface. A cap is fixed to the first face of the die and has a hole forming a fluidic path connecting the diaphragm with the outside world. A closing region, for example a support, a second cap, or another die, is fixed to the second face of the die. The closing region forms, together with the die and the cap, a stop structure configured to limit movements of the suspended region in a direction perpendicular to the first face.
Abstract translation: 一种MEMS器件，其中半导体材料的管芯具有第一面和第二面。 在模具中或模具上形成隔膜，并且面对第一表面。 帽固定在模具的第一面上，并且具有形成连接隔膜与外界的流体路径的孔。 关闭区域，例如支撑件，第二盖子或另一个模具，被固定到模具的第二面。 闭合区域与模具和盖一起形成止挡结构，其被构造成限制悬挂区域在垂直于第一面的方向上的移动。
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