Semiconductor device and method of manufacturing the same
    11.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US07576393B2

    公开(公告)日:2009-08-18

    申请号:US11476595

    申请日:2006-06-29

    IPC分类号: H01L23/62

    摘要: A semiconductor device comprises a pillar layer including first semiconductor pillars of a first conduction type and second semiconductor pillars of a second conduction type formed laterally, periodically and alternately. The first and second semiconductor pillars include a plurality of diffusion layers formed in a third semiconductor layer as coupled along the depth. The diffusion layers have lateral widths varied at certain periods along the depth. An average of the lateral widths of the diffusion layers in one certain period is made almost equal to another between different periods.

    摘要翻译: 半导体器件包括:柱层,其包括第一导电类型的第一半导体柱和第二导电类型的第二半导体柱,所述第二导电类型横向,周期性地和交替地形成。 第一和第二半导体柱包括沿着深度耦合形成在第三半导体层中的多个扩散层。 扩散层的横向宽度在沿深度的某些周期变化。 在一定时间段内扩散层的横向宽度的平均值在不同周期之间几乎等于另一个。

    SEMICONDUCTOR APPARATUS
    12.
    发明申请

    公开(公告)号:US20090090968A1

    公开(公告)日:2009-04-09

    申请号:US12243280

    申请日:2008-10-01

    IPC分类号: H01L29/78

    摘要: A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a second conductivity type provided in a surface portion of the semiconductor layer in a edge termination region outside a device region in which a main current path is formed in a vertical direction between the first main electrode and the second main electrode; and a plurality of buried semiconductor regions of the second conductivity type provided in the semiconductor layer in the edge termination region, spaced from the semiconductor regions, and spaced from each other. The buried semiconductor regions provided substantially at the same depth from the frontside of the semiconductor layer are numbered as first, second, . . . , n-th, sequentially from the one nearer to the device region, the n-th buried semiconductor regions provided at different depths from the frontside of the semiconductor layer are displaced toward the device region relative to the corresponding n-th semiconductor region, and the buried semiconductor region located deeper from the frontside of the semiconductor layer is displaced more greatly toward the device region.

    摘要翻译: 半导体装置包括:第一导电类型的半导体层; 设置在所述半导体层的前侧的第一主电极; 设置在所述半导体层的背面的第二主电极,所述背面与所述前侧相反; 在第一主电极和第二主电极之间沿垂直方向形成有主电流路径的器件区域外的边缘终端区域的半导体层的表面部分中设置的多个第二导电类型的半导体区域 ; 以及设置在边缘终端区域中的半导体层中的与半导体区域间隔开并且彼此间隔开的第二导电类型的多个掩埋半导体区域。 基本上与半导体层的前侧相同的深度设置的掩埋半导体区域被编号为第一,第二。 。 。 第n个从靠近器件区的一个顺序地,与半导体层的前侧不同的深度设置的第n个埋入半导体区域相对于相应的第n个半导体区域朝向器件区域移位, 位于半导体层的前侧较深的掩埋半导体区域朝向器件区域更大地移位。

    SEMICONDUCTOR APPARATUS
    13.
    发明申请

    公开(公告)号:US20080290403A1

    公开(公告)日:2008-11-27

    申请号:US12123072

    申请日:2008-05-19

    IPC分类号: H01L29/78

    摘要: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.

    摘要翻译: 半导体装置包括第一半导体层,设置在第一半导体层的主表面上的第二半导体层,设置在主表面上并与第二半导体层相邻的第三半导体层,设置在主体上的端接半导体层 在器件区域外的终端区域中的第一半导体层的表面,沟道阻挡层和沟道停止电极。 沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触,并且具有比端接半导体层更高的杂质浓度。 通道阻挡电极设置在通道阻挡层的表面的至少一部分上,并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

    POWER SEMICONDUCTOR DEVICE
    14.
    发明申请
    POWER SEMICONDUCTOR DEVICE 有权
    功率半导体器件

    公开(公告)号:US20080246085A1

    公开(公告)日:2008-10-09

    申请号:US12050405

    申请日:2008-03-18

    IPC分类号: H01L29/78

    摘要: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer that are provided above the first semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layers and connected to the third semiconductor layer; a fifth semiconductor layer; a control electrode; a gate insulating film; a first main electrode; and a second main electrode. An array period of the fourth semiconductor layers is larger than an array period of the second semiconductor layers. A thickness of a part of the gate insulating film disposed in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of a part of the gate insulating film disposed in the immediate upper region of the fourth semiconductor layer. Sheet impurity concentrations of the second semiconductor layer and the third semiconductor layer that are located in the central portion are higher than a sheet impurity concentration of the third semiconductor layer disposed in an immediately lower region of the fourth semiconductor layer.

    摘要翻译: 功率半导体器件包括:第一半导体层; 第二半导体层和第三半导体层,其设置在所述第一半导体层的上方,并且沿着与所述第一半导体层的上表面平行的方向配置; 多个第四半导体层,设置在所述第三半导体层的一些上部区域上,并连接到所述第三半导体层; 第五半导体层; 控制电极; 栅极绝缘膜; 第一主电极; 和第二主电极。 第四半导体层的阵列周期大于第二半导体层的阵列周期。 设置在第四半导体层之间的中心部分的直接上部区域中的栅极绝缘膜的一部分的厚度比设置在第四半导体层的直接上部区域中的栅极绝缘膜的一部分的厚度厚。 位于中心部分的第二半导体层和第三半导体层的片状杂质浓度高于设置在第四半导体层的紧邻下部区域中的第三半导体层的片状杂质浓度。

    SEMICONDUCTOR APPARATUS
    15.
    发明申请

    公开(公告)号:US20080179671A1

    公开(公告)日:2008-07-31

    申请号:US12020288

    申请日:2008-01-25

    IPC分类号: H01L29/78

    摘要: A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer in a device region and a termination region outside the device region; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, forming a periodic array structure; a field insulating film provided on the second first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer in the termination region; a first field plate electrode provided on the field insulating film and connected to the second main electrode or the control electrode; and a second field plate electrode. The second field plate electrode partly overlies the first field plate electrode through intermediary of an insulating film and extends on the field insulating film outside the first field plate electrode. The second field plate electrode is floating in potential.

    摘要翻译: 一种半导体装置,包括:第一第一导电型半导体层; 设置在器件区域中的第一第一导电型半导体层的主表面上的第二第一导电型半导体层和器件区域外的端接区域; 与第二第一导电型半导体层相邻的第三第二导电型半导体层,形成周期性阵列结构; 设置在终端区域中的第二第一导电型半导体层和第三第二导电型半导体层上的场绝缘膜; 设置在场绝缘膜上并连接到第二主电极或控制电极的第一场板电极; 和第二场板电极。 第二场板电极通过绝缘膜部分地覆盖在第一场极板电极上,并且在第一场极板电极外部的场绝缘膜上延伸。 第二场板电极浮置电位。

    Semiconductor device
    16.
    发明申请

    公开(公告)号:US20060231917A1

    公开(公告)日:2006-10-19

    申请号:US11399448

    申请日:2006-04-07

    IPC分类号: H01L29/00

    摘要: This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11

    Semiconductor device
    19.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US06977414B2

    公开(公告)日:2005-12-20

    申请号:US10460407

    申请日:2003-06-13

    摘要: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a pair of base regions of a second conductivity type selectively provided on a surface of the semiconductor layer; and source regions of a first conductivity type, each of the source regions being selectively provided on a surface of each of the base regions. The semiconductor device further comprises an electrical field reducing region of a second conductivity type selectively provided on the surface of the semiconductor layer between the pair of the base regions; a gate insulating film provided on the surface of the base regions; a pair of gate electrodes provided on the gate insulating film, each of the gate electrodes being provided on the surface of the base regions between the source region and the electrical field reducing region; and a source electrode connected to the source regions. The electrical field reducing region is isolated from both of the gate electrode and the source electrode.

    摘要翻译: 半导体器件包括:第一导电类型的半导体层; 选择性地设置在半导体层的表面上的一对第二导电类型的基极区; 以及第一导电类型的源极区域,每个源区域选择性地设置在每个基极区域的表面上。 所述半导体器件还包括选择性地设置在所述一对基极区域之间的所述半导体层的表面上的第二导电类型的电场减小区域; 设置在所述基底区域的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的一对栅电极,在所述源极区域和所述电场减少区域之间的所述基极区域的表面上设置各栅极电极; 以及与源极区域连接的源电极。 电场减少区域与栅极电极和源极电极隔离。

    Vertical type power mosfet having trenched gate structure
    20.
    发明授权
    Vertical type power mosfet having trenched gate structure 有权
    具有沟槽栅极结构的垂直型功率MOSFET

    公开(公告)号:US06787848B2

    公开(公告)日:2004-09-07

    申请号:US10184974

    申请日:2002-07-01

    IPC分类号: H01L2976

    摘要: A power MOSFET comprising a drain layer of a first conductivity type, a drift layer of the first conductivity type provided on the drain layer, a base layer of a first or a second conductivity type provided on the drift layer, a source region of the first conductivity type provided on the base layer, a gate insulating film formed on an inner wall surface of a trench penetrating the base layer and reaching at the drift layer, and a gate electrode provided on the gate insulating film inside the trench, wherein the gate insulating film is formed such that a portion thereof adjacent to the drift layer is thicker than a portion thereof adjacent to the base layer, and the drift layer has an impurity concentration gradient higher in the vicinity of the drain layer and lower in the vicinity of the source region along a depth direction of trench.

    摘要翻译: 一种功率MOSFET,包括第一导电类型的漏极层,设置在漏极层上的第一导电类型的漂移层,设置在漂移层上的第一或第二导电类型的基极层,第一导电类型的源极区域 设置在基底层上的导电类型,形成在穿过基底层并到达漂移层的沟槽的内壁表面上的栅极绝缘膜,以及设置在沟槽内部的栅极绝缘膜上的栅电极,其中栅极绝缘 膜形成为使得其与漂移层相邻的部分比与基底层相邻的部分厚,并且漂移层在漏极层附近具有较高的杂质浓度梯度,并且在源极附近较低 区域沿着沟槽的深度方向。