公开(公告)号：USD679308S1

公开(公告)日：2013-04-02

申请号：US29391234

申请日：2011-05-05

Applicant: Won-myung Park ,  Seung-hun Lee

Designer： Won-myung Park ,  Seung-hun Lee

公开(公告)号：US20130036970A1

公开(公告)日：2013-02-14

申请号：US13641694

申请日：2011-04-14

Applicant: Sun Hong Choi ,  Kwang Man Ko ,  Seung Hun Lee ,  Seung Ho Lee ,  Ho Chul Lee

Inventor： Sun Hong Choi ,  Kwang Man Ko ,  Seung Hun Lee ,  Seung Ho Lee ,  Ho Chul Lee

IPC: B05C13/00

CPC classification number: H01L21/6719 ,  C23C16/4584 ,  C23C16/4585 ,  C23C16/54 ,  H01L21/67126 ,  H01L21/68764 ,  H01L21/68771

Abstract: A substrate processing apparatus for deposition on a water seated therein is disclosed. The substrate processing apparatus includes a chamber having a reaction space, a lid provided on the chamber to selectively open or close the reaction space, a main disc accommodated in the chamber, on which at least one wafer is placed, and a drive device including a drive shaft to selectively rotate the main disc and a drive unit to drive the drive shaft. The drive shaft is separably coupled to the main disc to transmit drive force. When the lid is opened to expose the reaction space, the main disc is separated from the drive shaft and is discharged to the outside of the chamber in a state in which the wafer is placed thereon.

Abstract translation: 公开了一种用于沉积在其上的水上的基板处理装置。 基板处理装置包括具有反应空间的室，设置在室上的盖，以选择性地打开或关闭反应空间;容纳在室中的主盘，其上放置至少一个晶片;以及驱动装置， 驱动轴以选择性地旋转主盘和驱动单元以驱动驱动轴。 驱动轴可分离地联接到主盘以传递驱动力。 当盖打开以暴露反应空间时，主盘与驱动轴分离，并且在晶片被放置在其上的状态下被排出到室外。

公开(公告)号：US07615338B2

公开(公告)日：2009-11-10

申请号：US11298385

申请日：2005-12-08

Applicant: Geun Su Lee ,  Seung Chan Moon ,  Seung Hun Lee

Inventor： Geun Su Lee ,  Seung Chan Moon ,  Seung Hun Lee

IPC: G03C1/73 ,  G03F7/26 ,  G03F7/36

CPC classification number: G03F7/40

Abstract: A photoresist coating composition that includes a compound represented by Formula 1 and an aqueous solvent, and a method for forming a fine pattern by coating the composition on a photoresist pattern to effectively reduce a size of a photoresist contact hole and a space, which can be applied to all semiconductor processes.

Abstract translation: 包括由式1表示的化合物和水性溶剂的光致抗蚀剂涂料组合物，以及通过在光致抗蚀剂图案上涂覆该组合物以有效地减小光致抗蚀剂接触孔的尺寸和空间来形成精细图案的方法，其可以是 适用于所有半导体工艺。

公开(公告)号：US20090197036A1

公开(公告)日：2009-08-06

申请号：US11628527

申请日：2006-07-25

Applicant: Sung-chul Hwang ,  Jae-Wan Sung ,  Seung-Baik Nam ,  Seung-Hun Lee ,  Jong-Bum Kim ,  Bum-Soo Kim

Inventor： Sung-chul Hwang ,  Jae-Wan Sung ,  Seung-Baik Nam ,  Seung-Hun Lee ,  Jong-Bum Kim ,  Bum-Soo Kim

IPC: B32B3/06 ,  B32B27/40 ,  B32B38/04 ,  B32B21/08 ,  B32B21/04 ,  B32B37/12

CPC classification number: B32B21/14 ,  B32B3/06 ,  B32B7/02 ,  B32B7/12 ,  B32B21/02 ,  B32B21/042 ,  B32B21/13 ,  B32B2250/40 ,  B32B2255/08 ,  B32B2255/26 ,  B32B2307/584 ,  B32B2307/734 ,  B32B2419/04 ,  E04F15/02 ,  Y10T156/10 ,  Y10T156/1052 ,  Y10T428/24008 ,  Y10T428/31511 ,  Y10T428/31591 ,  Y10T428/31783 ,  Y10T428/3179 ,  Y10T428/31906 ,  Y10T428/31989

Abstract: Disclosed is a wood flooring containing laminated wood and high-density fiberboard using a symmetric structure and a process for manufacturing the same. The wood flooring includes a high-density fiberboard core layer and an upper laminated wood layer and lower laminated wood or veneer layer symmetrically stacked about the high-density fiberboard core layer to achieve a stable structure, and the lower laminated wood or veneer layer has a density of 100±30% of that of the upper laminated wood layer to keep the balance therebetween. With this configuration it is possible to completely eliminate deformation problems caused by variation of environmental conditions such as temperature, humidity, etc., and to impart the natural texture of raw lumber and high durability to the flooring surface.

Abstract translation: 公开了一种含有层叠木材和使用对称结构的高密度纤维板的木地板及其制造方法。 木地板包括高密度纤维板芯层和上部层压木材层以及围绕高密度纤维板芯层对称地堆叠的下层叠木材或单板层以实现稳定的结构，并且下部层压木材或单板层具有 密度为上层压木质层的100±30％，以保持它们之间的平衡。 通过这种结构，能够完全消除由诸如温度，湿度等的环境条件的变化引起的变形问题，并赋予原木的自然纹理和对地板表面的高耐久性。

公开(公告)号：US07161847B2

公开(公告)日：2007-01-09

申请号：US11030784

申请日：2005-01-07

Applicant: Seung Hun Lee

Inventor： Seung Hun Lee

IPC: G11C7/00

CPC classification number: G11C7/02 ,  G11C5/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093

Abstract: A data I/O apparatus for use in a memory device. The data I/O apparatus for use in the memory device performs data transmission using the same polarity when neighbor global I/O lines have opposite polarities to reduce coupling noise generated between global I/O lines acting as data I/O lines of a memory device, performs data recovery, and basically deletes the coupling noise, such that it reduces the failure rate of the memory device.

Abstract translation: 一种用于存储装置的数据I / O装置。 当相邻全局I / O线具有相反的极性时，用于存储装置的数据I / O装置使用相同的极性执行数据传输，以减少作为充当存储器的数据I / O线的全局I / O线之间产生的耦合噪声 设备，执行数据恢复，并基本上删除耦合噪声，从而降低存储器件的故障率。

公开(公告)号：USD421970S

公开(公告)日：2000-03-28

申请号：US100734

申请日：1999-02-17

Applicant: Seung-Hun Lee

Designer： Seung-Hun Lee

公开(公告)号：US5631871A

公开(公告)日：1997-05-20

申请号：US578151

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  B01F7/00 ,  B01F13/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5598371A

公开(公告)日：1997-01-28

申请号：US565292

申请日：1995-11-30

Applicant: Ho-Cheol Lee ,  Seung-Hun Lee

Inventor： Ho-Cheol Lee ,  Seung-Hun Lee

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  G11C13/00 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1078

Abstract: A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.

Abstract translation: 一种包括多个存储单元的半导体存储器件的数据输入/输出感测电路，该电路包括：存储单元的输入/输出线; 连接到存储单元外部的数据输入/输出端子; 连接在输入/输出线路和数据输入/输出端子之间的单个数据输入/输出线路; 感测单元，用于检测数据输入/输出线中是否提供有效数据，从而产生感测信号; 输出驱动单元，用于响应于感测信号将数据输入/输出线的数据发送到数据输入/输出端; 以及写入驱动单元，用于响应于感测信号输入数据输入/输出端子的数据。

公开(公告)号：US09190410B2

公开(公告)日：2015-11-17

申请号：US14466078

申请日：2014-08-22

Applicant: Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

Inventor： Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

Abstract translation: 一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一 以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成 第一外延层，以填充第一沟槽。

公开(公告)号：US20130295348A1

公开(公告)日：2013-11-07

申请号：US13979312

申请日：2012-01-11

Applicant: Dong Sik Jang ,  Seung Hun Lee

Inventor： Dong Sik Jang ,  Seung Hun Lee

IPC: B32B15/04

CPC classification number: B32B15/04 ,  B41M5/38214 ,  B41M2205/30 ,  B41M2205/38 ,  B44C1/1704 ,  B44C1/1712 ,  B44C1/1716 ,  B44C1/1729 ,  Y10T428/24851

Abstract: Disclosed is a transfer film which is transferred to an injection molding product. The transfer film includes a protective layer a printing layer which is stacked on the protective layer; a metal deposition layer which is deposited on the printing layer so as to have an island structure and thus to provide non-conductive property; and adhesive layer which is deposited on the metal deposition layer, thereby providing metal color and non-conductive property.

Abstract translation: 公开了转移到注射成型产品的转移膜。 转印膜包括保护层，层叠在保护层上的印刷层; 金属沉积层，其沉积在印刷层上以具有岛状结构，从而提供非导电性; 以及沉积在金属沉积层上的粘合剂层，从而提供金属颜色和非导电性。