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    Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method
    11.
    发明授权
    Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method 有权
    具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法

    公开(公告)号：US08344921B2

    公开(公告)日：2013-01-01

    申请号：US13072797

    申请日：2011-03-28

    Applicant: Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

    Inventor： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

    IPC: H03M3/00

    CPC classification number: H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

    Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.

    Abstract translation: Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。

    Delta-sigma analog-to-digital converter
    12.
    发明授权
    Delta-sigma analog-to-digital converter 有权
    Delta-sigma模数转换器

    公开(公告)号：US07893855B2

    公开(公告)日：2011-02-22

    申请号：US12485924

    申请日：2009-06-17

    Applicant: Sheng-Jui Huang

    Inventor： Sheng-Jui Huang

    IPC: H03M3/00

    CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/4565 ,  H03F3/45932 ,  H03F2200/408 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45514 ,  H03F2203/45562 ,  H03F2203/45594 ,  H03F2203/45644 ,  H03H11/1252 ,  H03H11/1291 ,  H03M1/0663 ,  H03M1/0809 ,  H03M1/206 ,  H03M1/361 ,  H03M1/806 ,  H03M3/424 ,  H03M3/448 ,  H03M3/464

    Abstract: An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and a second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.

    Abstract translation: 示例性连续时间Δ-Σ模数转换器包括环路滤波器，量化器，动态元件匹配电路，锁存器和数模转换器（DAC）。 环路滤波器包括串联耦合的多个积分器，包括第一积分器和第二积分器; 第一正反馈电阻元件，放置在第二积分器的第一输出节点与第一积分器的第一输入节点之间的第一正反馈路径中; 以及第一负反馈电阻元件，放置在第二积分器的第二输出节点与第一积分器的第二输入节点之间的第一负反馈路径中。 量化器使用多米诺量化器实现。 DAC包含多个DAC单元，每个DAC单元均具有电容性器件，电阻器件和耦合在电容器件和电阻器件之间的开关器件。

    PROCESSING APPARATUS FOR CALIBRATING ANALOG FILTER ACCORDING TO FREQUENCY-RELATED CHARACTERISTIC OF ANALOG FILTER, PROCESSING APPARATUS FOR GENERATING COMPENSATION PARAMETER USED TO CALIBRATE ANALOG FILTER, RELATED COMMUNICATION DEVICE, AND METHODS THEREOF
    13.
    发明申请
    PROCESSING APPARATUS FOR CALIBRATING ANALOG FILTER ACCORDING TO FREQUENCY-RELATED CHARACTERISTIC OF ANALOG FILTER, PROCESSING APPARATUS FOR GENERATING COMPENSATION PARAMETER USED TO CALIBRATE ANALOG FILTER, RELATED COMMUNICATION DEVICE, AND METHODS THEREOF 有权
    用于根据与模拟滤波器的频率相关特性来校准模拟滤波器的处理装置，用于生成用于校准模拟滤波器的补偿参数的处理装置，相关通信装置及其方法

    公开(公告)号：US20100253558A1

    公开(公告)日：2010-10-07

    申请号：US12420026

    申请日：2009-04-07

    Applicant: Pei-Wei Chen ,  Sheng-Jui Huang

    Inventor： Pei-Wei Chen ,  Sheng-Jui Huang

    IPC: H03M1/10 ,  H03K5/00

    CPC classification number: H04B1/0035 ,  H03H7/0153 ,  H03H7/03

    Abstract: A processing apparatus for calibrating an analog filter of a communication device in a digital domain is disclosed, wherein the analog filter is arranged to perform a filtering operation upon a communication signal in an analog domain. The processing apparatus includes a signal processing circuit and a digital filter. The signal processing circuit is used for transforming the communication signal between the digital domain and the analog domain. The digital filter is coupled to the signal processing circuit, and used for performing a filtering operation upon the communication signal in the digital domain, wherein a frequency response of the digital filter is arranged to compensate a frequency response of the analog filter according to at least a compensation parameter generated with reference to a frequency-related characteristic of the analog filter.

    Abstract translation: 公开了一种用于校准数字域中的通信设备的模拟滤波器的处理装置，其中模拟滤波器被布置为对模拟域中的通信信号执行滤波操作。 处理装置包括信号处理电路和数字滤波器。 信号处理电路用于对数字域和模拟域之间的通信信号进行变换。 数字滤波器耦合到信号处理电路，并用于对数字域中的通信信号执行滤波操作，其中数字滤波器的频率响应被布置为根据至少来补偿模拟滤波器的频率响应 参考模拟滤波器的频率相关特性产生的补偿参数。

    Operational amplifier and operating method thereof
    16.
    发明授权
    Operational amplifier and operating method thereof 有权
    运算放大器及其操作方法

    公开(公告)号：US07474242B2

    公开(公告)日：2009-01-06

    申请号：US11778645

    申请日：2007-07-16

    Applicant: Sheng-Jui Huang

    Inventor： Sheng-Jui Huang

    IPC: H03M3/00

    CPC classification number: H03F3/45192 ,  H03F1/26 ,  H03F2200/372 ,  H03F2203/45301 ,  H03F2203/45724

    Abstract: An operational amplifier is disclosed. The operational amplifier comprises an input stage and a loading stage. The input stage receives a differential input signal pair corresponding to a first frequency band. The loading stage is coupled to the input stage. The loading stage outputs an amplified differential output at output nodes. The loading stage comprises a flicker noise source and a modulating device. The modulating device is coupled to the flicker noise source. The modulating device modulates flicker noises into a second frequency band. The modulating device is not within a signal path.

    Abstract translation: 公开了一种运算放大器。 运算放大器包括输入级和加载级。 输入级接收对应于第一频带的差分输入信号对。 加载阶段耦合到输入级。 加载级在输出节点输出放大的差分输出。 加载阶段包括闪烁噪声源和调制装置。 调制装置耦合到闪烁噪声源。 调制装置将闪烁噪声调制成第二频带。 调制装置不在信号路径内。

    QUANTIZATION CIRCUIT HAVING VCO-BASED QUANTIZER COMPENSATED IN PHASE DOMAIN AND RELATED QUANTIZATION METHOD AND CONTINUOUS-TIME DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER
    17.
    发明申请
    QUANTIZATION CIRCUIT HAVING VCO-BASED QUANTIZER COMPENSATED IN PHASE DOMAIN AND RELATED QUANTIZATION METHOD AND CONTINUOUS-TIME DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER 有权
    具有相位补偿的基于VCO的量化器的量化电路和相关的量化方法和连续时间的三角形模拟数字转换器

    公开(公告)号：US20120112936A1

    公开(公告)日：2012-05-10

    申请号：US13189568

    申请日：2011-07-25

    Applicant: Sheng-Jui Huang

    Inventor： Sheng-Jui Huang

    IPC: H03M1/12 ,  H04N7/26

    CPC classification number: H03M1/502 ,  H03M3/424

    Abstract: A quantization circuit includes a quantizer and a compensation circuit. The quantizer includes a voltage-to-phase converter and a phase difference digitization block. The voltage-to-phase converter is arranged for generating a phase signal according to an input voltage. The phase difference digitization block is arranged for generating a quantization output according to a phase difference between a phase of the phase signal and a reference phase input. The compensation circuit is arranged for applying compensation to the phase difference digitization block according to the quantization output.

    Abstract translation: 量化电路包括量化器和补偿电路。 量化器包括电压 - 相位转换器和相位差数字化块。 电压 - 相位转换器被布置用于根据输入电压产生相位信号。 相位差数字化块被配置为根据相位信号的相位和参考相位输入之间的相位差产生量化输出。 补偿电路被配置为根据量化输出对相位差数字化块进行补偿。

    COMMUNICATION RECEIVER HAVING THREE FILTERS CONNECTED IN SERIES
    18.
    发明申请
    COMMUNICATION RECEIVER HAVING THREE FILTERS CONNECTED IN SERIES 审中-公开
    具有连接的三个过滤器的通信接收器

    公开(公告)号：US20110007845A1

    公开(公告)日：2011-01-13

    申请号：US12499081

    申请日：2009-07-07

    Applicant: Yen-Horng Chen ,  Sheng-Jui Huang

    Inventor： Yen-Horng Chen ,  Sheng-Jui Huang

    IPC: H04L25/06 ,  H04L27/06 ,  H04L27/22

    CPC classification number: H04B1/1027

    Abstract: A communication receiver includes a mixer, a filter group and an analog-to-digital converter. The mixer is used for mixing an input signal with a local oscillation signal to generate a mixed signal. The filter group is coupled to the mixer, and is used for filtering the mixed signal to generate a filtered signal, where the filter group includes a first one-pole filter, a second one-pole filter, and a complex-pole filter. The analog-to-digital converter is coupled to the filter group, and is used for performing an analog-to-digital converting operation on the filtered signal to generate a digital signal.

    Abstract translation: 通信接收机包括混频器，滤波器组和模数转换器。 混频器用于将输入信号与本地振荡信号混合以产生混合信号。 滤波器组耦合到混频器，并且用于对混合信号进行滤波以产生滤波信号，其中滤波器组包括第一单极滤波器，第二单极滤波器和复极滤波器。 模数转换器耦合到滤波器组，并且用于对经滤波的信号执行模数转换操作以产生数字信号。

    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER
    19.
    发明申请
    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER 有权
    DELTA-SIGMA模拟到数字转换器

    公开(公告)号：US20100066577A1

    公开(公告)日：2010-03-18

    申请号：US12485924

    申请日：2009-06-17

    Applicant: Sheng-Jui Huang

    Inventor： Sheng-Jui Huang

    IPC: H03M3/00

    CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/4565 ,  H03F3/45932 ,  H03F2200/408 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45514 ,  H03F2203/45562 ,  H03F2203/45594 ,  H03F2203/45644 ,  H03H11/1252 ,  H03H11/1291 ,  H03M1/0663 ,  H03M1/0809 ,  H03M1/206 ,  H03M1/361 ,  H03M1/806 ,  H03M3/424 ,  H03M3/448 ,  H03M3/464

    Abstract: An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and the first second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.

    Abstract translation: 示例性连续时间Δ-Σ模数转换器包括环路滤波器，量化器，动态元件匹配电路，锁存器和数模转换器（DAC）。 环路滤波器包括串联耦合的多个积分器，包括第一积分器和第二积分器; 第一正反馈电阻元件，放置在第二积分器的第一输出节点与第一积分器的第一输入节点之间的第一正反馈路径中; 以及第一负反馈电阻元件，放置在第二积分器的第二输出节点与第一积分器的第一第二输入节点之间的第一负反馈路径中。 量化器使用多米诺量化器实现。 DAC包含多个DAC单元，每个DAC单元均具有电容性器件，电阻器件和耦合在电容器件和电阻器件之间的开关器件。

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