公开(公告)号：US06865127B2

公开(公告)日：2005-03-08

申请号：US10412264

申请日：2003-04-14

申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka

发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C11/4076 ,  G11C2207/2281

摘要： The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.

公开(公告)号：US20050018461A1

公开(公告)日：2005-01-27

申请号：US10918421

申请日：2004-08-16

申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C11/401 ,  G11C29/12 ,  G11C29/14 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56 ,  G11C19/08

CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C11/41 ,  G11C29/14 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.

摘要翻译： 控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中， 内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中， 响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

公开(公告)号：US06191990B1

公开(公告)日：2001-02-20

申请号：US09507785

申请日：2000-02-22

申请人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

发明人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

IPC分类号： G11C702

CPC分类号： G11C7/18 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/11 ,  H01L28/75

摘要： A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

摘要翻译： 一种半导体集成电路器件具有存储器阵列，该存储器阵列包括将读出放大器中的动态存储单元读出的小电压放大到位线和选择位线的列开关MOSFET的读出放大器的MOSFET，包括用于读出的主放大器的读/写部分 来自由列开关选择的存储器单元的存储数据，以及实现与读/写部分的数据的输入/输出操作的逻辑电路。 两个电容器具有第一电极，其对应于具有与动态存储单元的存储电容器相同结构的平板电极的第一电极和作为存储电容器的多个共同连接的存储节点的第二电极串联连接设置 到读/写部分，并连接在读/写部分的操作电压线之间。

公开(公告)号：US07113434B2

公开(公告)日：2006-09-26

申请号：US10823664

申请日：2004-04-14

申请人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

发明人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

摘要翻译： 在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。 在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块 时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍 的时钟信号。

公开(公告)号：US06714477B2

公开(公告)日：2004-03-30

申请号：US10187947

申请日：2002-07-03

申请人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

发明人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4093

摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

摘要翻译： 读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置， 输出无能力状态不存在。 这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此 提高读取数据输出操作的吞吐量。

公开(公告)号：US06570800B2

公开(公告)日：2003-05-27

申请号：US09756800

申请日：2001-01-10

申请人： Yousuke Tanaka ,  Masahiro Katayama ,  Yuji Yokoyama ,  Hiroshi Akasaki ,  Shuichi Miyaoka ,  Toru Kobayashi

发明人： Yousuke Tanaka ,  Masahiro Katayama ,  Yuji Yokoyama ,  Hiroshi Akasaki ,  Shuichi Miyaoka ,  Toru Kobayashi

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4096

摘要： The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.

摘要翻译： 以时钟信号周期多次的周期改变的列地址选通信号（CAS）被输入到存储块（MBK0〜MBKn）。 当列地址信号（CASADR）为“0”时，每个周期输出从存储单元阵列（10）读出并与并行/串行转换器电路（21）并行/串行转换的多个串行数据， 改变了 并行数据输入到存储器块，并且与时钟信号周期同步地由串行/并行转换器电路（25）串行/并行转换的并行数据被写入存储单元阵列中。 以这种方式，列地址选通信号的访问规范每时钟信号的n个周期改变一次，从而允许更快速的存储器操作。

公开(公告)号：US06430103B2

公开(公告)日：2002-08-06

申请号：US09775544

申请日：2001-02-05

申请人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

发明人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4093

摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

摘要翻译： 读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置， 输出无能力状态不存在。 这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此 提高读取数据输出操作的吞吐量。

公开(公告)号：US5265060A

公开(公告)日：1993-11-23

申请号：US832334

申请日：1992-02-07

申请人： Shuichi Miyaoka

发明人： Shuichi Miyaoka

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/413

CPC分类号： G11C7/1057 ,  G11C11/413 ,  G11C7/00 ,  G11C7/1051

摘要： In semiconductor circuits, and particularly in memories, it is often desirable to use bipolar transistors for speed together with MOS elements. However, although the bipolar transistors are useful for speed considerations, they undesirably significantly increase the power consumption of the overall circuit. Accordingly, to reduce power consumption, a bipolar/MOSFET arrangement is provided wherein MOSFETs are used as current sources to supply operation currents to the bipolar transistors only during the periods of their operation. Thus, a semiconductor integrated circuit device is achieved featuring a high operation speed yet consuming reduced amounts of electric power. Additionally, power consumption can be further reduced by providing a time serial operation for actuation of the MOSFETs in different peripheral circuits for a memory array.

摘要翻译： 在半导体电路中，特别是在存储器中，通常希望与MOS元件一起使用双极晶体管。 然而，虽然双极晶体管对于速度考虑是有用的，但是它们不利地显着增加了整个电路的功耗。 因此，为了降低功耗，提供了一种双极/ MOSFET布置，其中MOSFET仅在其工作期间用作电流源以向双极型晶体管提供工作电流。 因此，实现了具有高操作速度但消耗减少的电力量的半导体集成电路器件。 此外，通过提供用于在用于存储器阵列的不同外围电路中的MOSFET的驱动的时间串行操作，可以进一步降低功耗。