公开(公告)号：US06735129B2

公开(公告)日：2004-05-11

申请号：US10153525

申请日：2002-05-24

申请人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

发明人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

IPC分类号： G11C700

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

摘要翻译： 在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。 在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块 时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍 的时钟信号。

公开(公告)号：US07113434B2

公开(公告)日：2006-09-26

申请号：US10823664

申请日：2004-04-14

申请人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

发明人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

摘要翻译： 在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。 在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块 时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍 的时钟信号。

公开(公告)号：US06570800B2

公开(公告)日：2003-05-27

申请号：US09756800

申请日：2001-01-10

申请人： Yousuke Tanaka ,  Masahiro Katayama ,  Yuji Yokoyama ,  Hiroshi Akasaki ,  Shuichi Miyaoka ,  Toru Kobayashi

发明人： Yousuke Tanaka ,  Masahiro Katayama ,  Yuji Yokoyama ,  Hiroshi Akasaki ,  Shuichi Miyaoka ,  Toru Kobayashi

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4096

摘要： The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.

摘要翻译： 以时钟信号周期多次的周期改变的列地址选通信号（CAS）被输入到存储块（MBK0〜MBKn）。 当列地址信号（CASADR）为“0”时，每个周期输出从存储单元阵列（10）读出并与并行/串行转换器电路（21）并行/串行转换的多个串行数据， 改变了 并行数据输入到存储器块，并且与时钟信号周期同步地由串行/并行转换器电路（25）串行/并行转换的并行数据被写入存储单元阵列中。 以这种方式，列地址选通信号的访问规范每时钟信号的n个周期改变一次，从而允许更快速的存储器操作。

公开(公告)号：US06714477B2

公开(公告)日：2004-03-30

申请号：US10187947

申请日：2002-07-03

申请人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

发明人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4093

摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

摘要翻译： 读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置， 输出无能力状态不存在。 这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此 提高读取数据输出操作的吞吐量。

公开(公告)号：US06430103B2

公开(公告)日：2002-08-06

申请号：US09775544

申请日：2001-02-05

申请人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

发明人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4093

摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

摘要翻译： 读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置， 输出无能力状态不存在。 这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此 提高读取数据输出操作的吞吐量。

公开(公告)号：US06191990B1

公开(公告)日：2001-02-20

申请号：US09507785

申请日：2000-02-22

申请人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

发明人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

IPC分类号： G11C702

CPC分类号： G11C7/18 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/11 ,  H01L28/75

摘要： A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

摘要翻译： 一种半导体集成电路器件具有存储器阵列，该存储器阵列包括将读出放大器中的动态存储单元读出的小电压放大到位线和选择位线的列开关MOSFET的读出放大器的MOSFET，包括用于读出的主放大器的读/写部分 来自由列开关选择的存储器单元的存储数据，以及实现与读/写部分的数据的输入/输出操作的逻辑电路。 两个电容器具有第一电极，其对应于具有与动态存储单元的存储电容器相同结构的平板电极的第一电极和作为存储电容器的多个共同连接的存储节点的第二电极串联连接设置 到读/写部分，并连接在读/写部分的操作电压线之间。

公开(公告)号：US10020511B2

公开(公告)日：2018-07-10

申请号：US14426799

申请日：2012-09-10

申请人： Tatsuya Hashimoto ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto

发明人： Tatsuya Hashimoto ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto

IPC分类号： H01M4/62 ,  H01M10/052 ,  H01M4/13 ,  H01M4/139

CPC分类号： H01M4/62 ,  H01M4/13 ,  H01M4/139 ,  H01M4/621 ,  H01M4/622 ,  H01M10/052 ,  H01M2220/20 ,  Y02E60/122 ,  Y02T10/7011

摘要： This invention provides a lithium secondary battery that comprises a positive electrode comprising a positive electrode active material layer and a negative electrode comprising a negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are placed to face each other. The negative electrode active material layer has an area A comprising a non-positive-electrode-facing portion that does not face the positive electrode active material layer. The area A comprises a negative electrode active material, a hot-melt binder and a temperature-sensitive thickener. The hot-melt binder has a melting point and the temperature-sensitive thickener has a gelation temperature both in a range of 45° C. to 100° C.

公开(公告)号：US08562367B2

公开(公告)日：2013-10-22

申请号：US13270476

申请日：2011-10-11

申请人： Yuji Yokoyama

发明人： Yuji Yokoyama

IPC分类号： H01R13/62

CPC分类号： H01R12/714 ,  G01R1/0466 ,  G01R31/2863 ,  H01R13/62933

摘要： A socket for electrical part mounted on the wiring substrate to accommodate an electrical part. The present invention comprises a socket body, a floating plate and a holding structure. The socket body has a contact pin unit comprising a unit body in which the plural contact pins are mounted. The floating plate is mounted on upper side of the unit body to accommodate the electrical part, and comprises through holes into which the upper side contact portions of contact pins are inserted. The holding structure holds the floating plate in a descended state when the socket for the electrical part is not yet mounted on the wiring substrate, and releases the holding state of floating plate and makes the floating plate to be capable of moving vertically under the state of being urged upward when the socket for the electrical part is mounted on the wiring substrate.

摘要翻译： 用于电气部件的插座，安装在布线基板上以容纳电气部件。 本发明包括插座主体，浮动板和保持结构。 插座本体具有接触针单元，该接触针单元包括其中安装有多个接触针的单元体。 浮板安装在单元主体的上侧以容纳电气部件，并且包括插孔的上侧接触部分的通孔。 当电气部件的插座尚未安装在布线基板上时，保持结构将浮动板保持在下降状态，并且释放浮板的保持状态并使浮板能够在状态下垂直移动 当电气部件的插座安装在布线基板上时被向上推动。

公开(公告)号：US06936510B2

公开(公告)日：2005-08-30

申请号：US10388454

申请日：2003-03-17

申请人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

发明人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10

CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10817 ,  H01L28/91

摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.

摘要翻译： 一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

公开(公告)号：US20130157096A1

公开(公告)日：2013-06-20

申请号：US13820743

申请日：2011-09-16

申请人： Yasushi Nakagiri ,  Hiroaki Furuta ,  Yasuhiko Hina ,  Yuji Yokoyama ,  Shinpei Yamagami ,  Akira Nagasaki ,  Norihiro Yamamoto

发明人： Yasushi Nakagiri ,  Hiroaki Furuta ,  Yasuhiko Hina ,  Yuji Yokoyama ,  Shinpei Yamagami ,  Akira Nagasaki ,  Norihiro Yamamoto

IPC分类号： H01M10/0587

CPC分类号： H01M10/0587 ,  H01M2/1673 ,  H01M2/18 ,  H01M4/667 ,  H01M4/70 ,  H01M10/0431

摘要： Disclosed is a non-aqueous electrolyte secondary battery including: a spirally-wound electrode group including a continuous first electrode, a continuous second electrode, and a continuous separator interposed between the first electrode and the second electrode; and a non-aqueous electrolyte. The first electrode includes a sheet-like first current collector, and a first active material layer formed on a surface of the first current collector; and the second electrode includes a sheet-like second current collector, and a second active material layer formed on a surface of the second current collector. In the electrode group, the winding terminal end of the first electrode faces the second electrode on the further outer peripheral side, with the separator interposed therebetween. The facing site of the second electrode where the second electrode faces the winding terminal end of the first electrode is reinforced with a reinforcing component for supplementing the thickness of the second electrode.

摘要翻译： 本发明公开了一种非水电解质二次电池，包括：螺旋卷绕电极组，包括连续的第一电极，连续的第二电极和介于所述第一电极和所述第二电极之间的连续隔膜; 和非水电解质。 第一电极包括片状第一集电体和形成在第一集电体的表面上的第一活性物质层; 并且所述第二电极包括片状的第二集电体和形成在所述第二集电体的表面上的第二活性物质层。 在电极组中，第一电极的绕组末端在另外的外周侧面对第二电极，隔膜间隔开。 第二电极的面对第一电极的绕组末端的第二电极的面对部位用用于补充第二电极的厚度的增强部件来增强。