公开(公告)号：US07000207B2

公开(公告)日：2006-02-14

申请号：US10820356

申请日：2004-04-08

Applicant: Prakash Gothoskar ,  Margaret Ghiron ,  Vipulkumar Patel ,  Robert Keith Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

Inventor： Prakash Gothoskar ,  Margaret Ghiron ,  Vipulkumar Patel ,  Robert Keith Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A system and method for providing the layout of non-Manhattan shaped integrated circuit elements using a Manhattan layout system utilizes a plurality of minimal sized polygons (e.g., rectangles) to fit within the boundaries of the non-Manhattan element. The rectangles are fit such that at least one vertex of each rectangle coincides with a grid point on the Manhattan layout system. Preferably, the rectangles are defined by using the spacing being adjacent grid points as the height of each rectangle. As the distance between adjacent grid points decreases, the layout better matches the actual shape of the non-Manhattan element. The system and method then allows for electrical and optical circuit elements to be laid out simultaneously, using the same layout software and equipment.

Abstract translation: 使用曼哈顿布局系统提供非曼哈顿形集成电路元件的布局的系统和方法利用多个最小尺寸的多边形（例如，矩形）来装配在非曼哈顿元件的边界内。 矩形被配合成使得每个矩形的至少一个顶点与曼哈顿布局系统上的网格点重合。 优选地，通过使用相邻网格点的间隔作为每个矩形的高度来定义矩形。 随着相邻网格点之间的距离减小，布局更好地匹配非曼哈顿元素的实际形状。 然后，系统和方法可以使用相同的布局软件和设备同时布置电气和光学电路元件。

公开(公告)号：US06980720B2

公开(公告)日：2005-12-27

申请号：US10818415

申请日：2004-04-05

Applicant: Prakash Gothoskar ,  Margaret Ghiron ,  Vipulkumar Patel ,  Robert Keith Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

Inventor： Prakash Gothoskar ,  Margaret Ghiron ,  Vipulkumar Patel ,  Robert Keith Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/26 ,  G02B6/32

CPC classification number: G02B6/1228 ,  G02B2006/12097

Abstract: A low loss coupling arrangement between a slab/strip waveguide and a rib waveguide in an optical waveguiding structure formed on a silicon-on-insulator (SOI) platform utilizes tapered sections at the input and/or output of the rib waveguide to reduce loss. Optical reflections are reduced by using silicon tapers (either vertical tapers, horizontal tapers, or two-dimensional tapers) that gradually transition the effective index seen by an optical signal propagating along the slab/strip waveguide and subsequently into and out of the rib waveguide. Loss can be further reduced by using adiabatically contoured silicon regions at the input and output of the rib waveguide to reduce mode mismatch between the slab/strip waveguide and rib waveguide. In a preferred embodiment, concatenated tapered and adiabatic sections can be used to provide for reduced optical reflection loss and reduced optical mode mismatch.

Abstract translation: 形成在绝缘体上硅（SOI）平台上的光波导结构中的板/条波导和肋波导之间的低损耗耦合布置在肋波导的输入和/或输出处利用锥形部分来减少损耗。 通过使用沿着板/条波导传播的随后进入和离开肋波导的光信号逐渐转变的有效折射率的硅锥（垂直锥度，水平锥度或二维锥度）来减少光学反射。 通过在肋波导的输入和输出处使用绝热的轮廓的硅区域来减少损耗，以减少板/波导管和肋波导之间的模式失配。 在优选实施例中，级联的锥形和绝热部分可用于提供减少的光学反射损失和减小的光学模式失配。

公开(公告)号：US20050236619A1

公开(公告)日：2005-10-27

申请号：US11169932

申请日：2005-06-29

Applicant: Vipulkumar Patel ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski

Inventor： Vipulkumar Patel ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski

IPC: H01L27/12 ,  H01L27/144 ,  H01L29/04

CPC classification number: H01L27/1443 ,  H01L27/1203

Abstract: A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.

公开(公告)号：US20050201683A1

公开(公告)日：2005-09-15

申请号：US11054205

申请日：2005-02-09

Applicant: Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  Kalpendu Shastri ,  Katherine Yanushefski

Inventor： Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  Kalpendu Shastri ,  Katherine Yanushefski

IPC: G02B6/122 ,  G02B6/14 ,  G02B6/26 ,  G02B6/34 ,  G02B6/42

CPC classification number: G02B6/1228 ,  G02B6/4204

Abstract: An arrangement for providing optical coupling between a free-space propagating optical signal and an ultrathin silicon waveguide formed in an upper silicon layer of a silicon-on-insulator (SOI) structure includes a silicon nanotaper structure formed in the upper silicon layer (SOI layer) of the SOI structure and coupled to the ultrathin silicon waveguide. A dielectric waveguide coupling layer, with a refractive index greater than the index of the dielectric insulating layer but less than the refractive index of silicon, is disposed so as to overly a portion of the dielectric insulating layer in a region where an associated portion of the SOI layer has been removed. An end portion of the dielectric waveguide coupling layer is disposed to overlap an end section of the silicon nanotaper to form a mode conversion region between the free-space propagating optical signal and the ultrathin silicon waveguide. A free-space optical coupling arrangement (such as a prism or grating) is disposed over the dielectric waveguide coupling layer and used to couple a propagating optical signal between free space and the dielectric waveguide coupling layer and thereafter into the ultrathin silicon waveguide.

Abstract translation: 用于在自由空间传播的光信号和形成在绝缘体上硅（SOI））结构的上硅层中的超薄硅波导之间提供光耦合的装置包括形成在上硅层（SOI层）中的硅纳米锥结构 ）和耦合到超薄硅波导。 具有大于介电绝缘层的折射率但小于硅的折射率的折射率的介质波导耦合层被布置成过度地在介电绝缘层的一部分中的相关部分 SOI层已被去除。 电介质波导耦合层的端部设置成与硅纳米锥的端部部分重叠以在自由空间传播的光信号和超薄硅波导之间形成模式转换区域。 自由空间光耦合装置（诸如棱镜或光栅）设置在介质波导耦合层之上，用于将传播的光信号耦合在自由空间与介质波导耦合层之间，然后耦合到超薄硅波导中。

公开(公告)号：US20050179986A1

公开(公告)日：2005-08-18

申请号：US11042774

申请日：2005-01-24

Applicant: Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  David Piede ,  Kalpendu Shastri ,  Katherine Yanushefski

Inventor： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  David Piede ,  Kalpendu Shastri ,  Katherine Yanushefski

IPC: G02B26/00 ,  G02F1/00 ,  G02F1/025

CPC classification number: G02F1/025 ,  G02F2202/32

Abstract: An SOI-based photonic bandgap (PBG) electro-optic device utilizes a patterned PBG structure to define a two-dimensional waveguide within an active waveguiding region of the SOI electro-optic device. The inclusion of the PBG columnar arrays within the SOI structure results in providing extremely tight lateral confinement of the optical mode within the waveguiding structure, thus significantly reducing the optical loss. By virtue of including the PBG structure, the associated electrical contacts may be placed in closer proximity to the active region without affecting the optical performance, thus increasing the switching speed of the electro-optic device. The overall device size, capacitance and resistance are also reduced as a consequence of using PBGs for lateral mode confinement.

Abstract translation: 基于SOI的光子带隙（PBG）电光器件利用图案化的PBG结构来在SOI电光器件的有源波导区域内限定二维波导。 在SOI结构中包含PBG柱状阵列导致在波导结构内提供光学模式的非常紧密的侧向约束，从而显着减少光学损耗。 通过包括PBG结构，相关联的电触点可以放置在更接近有源区域而不影响光学性能，从而增加电光器件的切换速度。 由于使用PBG用于横向模式限制，整个装置尺寸，电容和电阻也减小。

公开(公告)号：US06897498B2

公开(公告)日：2005-05-24

申请号：US10772724

申请日：2004-02-05

Applicant: Prakash Gothoskar ,  Margaret Ghiron ,  Vipulkumar Patel ,  Robert Keith Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

Inventor： Prakash Gothoskar ,  Margaret Ghiron ,  Vipulkumar Patel ,  Robert Keith Montgomery ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

IPC: H01L20060101 ,  H01L21/302 ,  H01L27/148 ,  H01L31/00

CPC classification number: G02B6/125 ,  B82Y20/00 ,  G02B6/1225 ,  G02B6/1226 ,  G02B6/1228 ,  G02F1/025 ,  G02F2201/58 ,  H01L31/02327 ,  H01L31/035281 ,  H01L31/03682 ,  H01L31/1808 ,  Y02E10/546

Abstract: A photodetector for use with relatively thin (i.e., sub-micron) silicon optical waveguides formed in a silicon-on-insulator (SOI) structure comprises a layer of poly-germanium disposed to couple at least a portion of the optical signal propagating along the silicon optical waveguide. Tight confinement of the optical signal within the waveguide structure allows for efficient evanescent coupling into the poly-germanium detector. The silicon optical waveguide may comprise any desired geometry, with the poly-germanium detector formed to either cover a portion of the waveguide, or be butt-coupled to an end portion of the waveguide. When covering a portion of the waveguide, poly-germanium detector may comprise a “wrap-around” geometry to cover the side and top surfaces of the optical waveguide, with electrical contacts formed at opposing ends of the detector.

Abstract translation: 用于在绝缘体上硅（SOI）结构中形成的相对较薄的（即亚微米）硅光波导的光电检测器包括一层聚锗，其设置成耦合沿着所述光纤传播的光信号的至少一部分 硅光波导。 波导结构内的光信号的紧密限制允许有效的ev逝耦合到聚锗检测器中。 硅光波导可以包括任何期望的几何形状，其中聚锗检测器形成为覆盖波导的一部分，或者与波导的端部对接。 当覆盖波导的一部分时，聚锗检测器可以包括覆盖光波导的侧表面和顶表面的“环绕”几何形状，其中电触点形成在检测器的相对端。

公开(公告)号：US06845198B2

公开(公告)日：2005-01-18

申请号：US10795748

申请日：2004-03-08

Applicant: Robert Keith Montgomery ,  Margaret Ghiron ,  Prakash Gothoskar ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

Inventor： Robert Keith Montgomery ,  Margaret Ghiron ,  Prakash Gothoskar ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski

IPC: G02F1/025 ,  G02F1/225 ,  G02B6/26

CPC classification number: G02F1/025 ,  G02B2006/12142 ,  G02B2006/12159 ,  G02F1/2257

Abstract: A silicon-based electro-optic modulator is based on forming a gate region of a first conductivity to partially overly a body region of a second conductivity type, with a relatively thin dielectric layer interposed between the contiguous portions of the gate and body regions. The modulator may be formed on an SOI platform, with the body region formed in the relatively thin silicon surface layer of the SOI structure and the gate region formed of a relatively thin silicon layer overlying the SOI structure. The doping in the gate and body regions is controlled to form lightly doped regions above and below the dielectric, thus defining the active region of the device. Advantageously, the optical electric field essentially coincides with the free carrier concentration area in this active device region. The application of a modulation signal thus causes the simultaneous accumulation, depletion or inversion of free carriers on both sides of the dielectric at the same time, resulting in high speed operation.

Abstract translation: 基于硅的电光调制器基于形成第一导电性的栅极区域，以部分地超过第二导电类型的体区，其中相对薄的电介质层插入在栅极和主体区域的邻接部分之间。 调制器可以形成在SOI平台上，其中主体区域形成在SOI结构的相对薄的硅表面层中，并且栅极区域由覆盖SOI结构的相对薄的硅层形成。 控制栅极和体区中的掺杂以形成电介质上方和下方的轻掺杂区域，从而限定器件的有源区。 有利地，光电场基本上与该有源器件区域中的自由载流子浓度区域重合。 因此，调制信号的应用同时导致电介质两侧的自由载流子的同时累积，消耗或反转，导致高速运行。

公开(公告)号：US20130182996A1

公开(公告)日：2013-07-18

申请号：US13737029

申请日：2013-01-09

Applicant: Kalpendu Shastri ,  Soham Pathak ,  John Fangman ,  Vipulkumar Patel ,  Kishor Desai ,  Ravinder Kachru

Inventor： Kalpendu Shastri ,  Soham Pathak ,  John Fangman ,  Vipulkumar Patel ,  Kishor Desai ,  Ravinder Kachru

IPC: G02B6/42 ,  G02B6/12

CPC classification number: G02B6/42 ,  G02B6/12 ,  G02B6/3886 ,  G02B6/4214 ,  G02B6/4259 ,  G02B6/4292 ,  Y10T29/49155

Abstract: An apparatus for providing releasable attachment between a fiber connector and an opto-electronic assembly, the opto-electronic assembly utilizing an interposer substrate to support a plurality of opto-electronic components that generates optical output signals and receives optical input signals. An enclosure is used to cover the interposer substrate and includes a transparent region through which the optical output and input signals pass unimpeded. A magnetic connector component is attached to the lid and positioned to surround the transparent region, with a fiber connector for supporting one or more optical fibers magnetically attached to the connector component by virtue of a metallic component contained in the fiber connector. This arrangement provides releasable attachment of the fiber connector to the enclosure in a manner where the optical output and input signals align with the optical fibers in the connector.

Abstract translation: 一种用于在光纤连接器和光电子组件之间提供可释放附件的装置，所述光电组件利用插入器基板来支撑产生光输出信号并接收光输入信号的多个光电元件。 外壳用于覆盖插入器基板，并且包括透明区域，光输出和输入信号通过该透明区域畅通无阻。 磁性连接器部件附接到盖子并且被定位成围绕透明区域，光纤连接器用于通过光纤连接器中包含的金属部件来支撑一个或多个磁性地附接到连接器部件的光纤。 这种布置以光输出和输入信号与连接器中的光纤对准的方式提供光纤连接器到外壳的可释放附接。

公开(公告)号：US20080253713A1

公开(公告)日：2008-10-16

申请号：US12157630

申请日：2008-06-12

Applicant: David Piede ,  Prakash Gothoskar ,  Margaret Ghiron ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  Kalpendu Shastri ,  Katherine A. Yanushefski

Inventor： David Piede ,  Prakash Gothoskar ,  Margaret Ghiron ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  Kalpendu Shastri ,  Katherine A. Yanushefski

IPC: G02B6/12

CPC classification number: G02B6/12004 ,  G02B6/125 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12104 ,  G02B2006/12176 ,  G02B2006/12195

Abstract: An arrangement for providing optical crossovers between waveguides formed in an SOI-based structure utilize a patterned geometry in the SOI structure that is selected to reduce the effects of crosstalk in the area where the signals overlap. Preferably, the optical signals are fixed to propagate along orthogonal directions (or are of different wavelengths) to minimize the effects of crosstalk. The geometry of the SOI structure is patterned to include predetermined tapers and/or reflecting surfaces to direct/shape the propagating optical signals. The patterned waveguide regions within the optical crossover region may be formed to include overlying polysilicon segments to further shape the propagating beams and improve the coupling efficiency of the crossover arrangement.

Abstract translation: 用于在基于SOI的结构中形成的波导之间提供光学交叉的装置利用SOI结构中的图案化几何形状，其被选择以减少信号重叠的区域中串扰的影响。 优选地，光信号被固定以沿着正交方向（或不同波长）传播，以最小化串扰的影响。 SOI结构的几何形状被图案化以包括预定的锥形和/或反射表面以引导/形成传播的光学信号。 光学交叉区域内的图案化波导区域可以形成为包括覆盖多晶硅段，以进一步使传播波束成形，并提高交叉布置的耦合效率。

公开(公告)号：US20050289490A1

公开(公告)日：2005-12-29

申请号：US11159283

申请日：2005-06-22

Applicant: Kalpendu Shastri ,  Soham Pathak ,  Prakash Gothoskar ,  Paulius Mosinskis ,  Bipin Dama

Inventor： Kalpendu Shastri ,  Soham Pathak ,  Prakash Gothoskar ,  Paulius Mosinskis ,  Bipin Dama

IPC: G06F17/50 ,  G06G7/62

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).

Abstract translation: 计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。 为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。 一旦行为逻辑设计完成，结果将被合并并共同模拟。 为电路中的每种不同类型的元件开发和验证物理布局设计。 然后将单独的物理布局共同验证，以评估整体物理设计的属性。 将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。 一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。