公开(公告)号：US08692585B2

公开(公告)日：2014-04-08

申请号：US13243351

申请日：2011-09-23

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03B1/00 ,  H03K3/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  H03K19/018521 ,  H03K19/018585

Abstract: A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.

Abstract translation: 半导体集成电路包括：第一输出驱动器，被配置为驱动第一比较信号，该第一比较信号是通过将耦合到外部电阻器的焊盘的电压与上限参考电压进行比较而产生的，根据由上拉代码确定的驱动能力 和下拉代码，并将驱动信号作为第一输出数据输出; 以及第二输出驱动器，被配置为根据由所述上拉代码和所述下拉码确定的驾驶性能来驱动通过将所述垫的电压与下限参考电压进行比较而产生的第二比较信号，以及 输出驱动信号作为第二输出数据。

公开(公告)号：US20130257474A1

公开(公告)日：2013-10-03

申请号：US13615373

申请日：2012-09-13

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: H03K19/003

CPC classification number: H03K19/0005

Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.

Abstract translation: 提供半导体模块。 半导体模块包括具有一个或多个等级的半导体芯片。 半导体模块包括模式寄存器，其被配置为存储根据等级的数量来设置或确定其逻辑电平的第一信息信号，以及配置用于产生用于激活ODT电路的内部控制信号的片上终端（ODT）控制器 响应于第一信息信号。 内部控制信号在读操作期间被使能，或者在写操作期间被禁止。

公开(公告)号：US08483408B2

公开(公告)日：2013-07-09

申请号：US12283774

申请日：2008-09-16

Applicant: Tae-Jin Kang

Inventor： Tae-Jin Kang

IPC: H03G5/00

CPC classification number: H04R3/04 ,  H03G5/025 ,  H04M1/6016 ,  H04M1/72572

Abstract: A mobile communication device and a method of setting tone color, which allow a user to set the tone color of received sound. Provided are a normal mode, which sets the equalizer using GCF standards stored in an internal memory or equalizer setting values selected by a provider, a country-specific mode, which uses country-specific setting, and a user mode, in which a user can set frequency-specific gains of the received sound, and one mode is selected from the provided mode, so that the tone color of the received sound can be adjusted according to the selection. Telephone speech quality can be optimized for user preference, network environments and language characteristics.

公开(公告)号：USRE44230E1

公开(公告)日：2013-05-21

申请号：US13367023

申请日：2012-02-06

Applicant: Tae-Jin Kang

Inventor： Tae-Jin Kang

IPC: G11C8/00

CPC classification number: G11C7/222 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract translation: 一种时钟信号产生装置，用于产生用于与来自半导体存储器件的外部时钟信号同步输出数据的参考时钟信号，包括：时钟信号产生单元，用于接收内部时钟信号以根据控制产生参考时钟信号 信号; 以及用于基于读取命令，写入命令和外部地址产生控制信号的控制单元。

公开(公告)号：US08379475B2

公开(公告)日：2013-02-19

申请号：US12824864

申请日：2010-06-28

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C7/1018 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

Abstract: A clock control circuit is presented for reducing unnecessary current consumption. The clock control circuit includes a write enable signal generation unit and a clock enable signal generation unit. The write enable signal generation unit is configured to generate a first write enable signal, which is enabled during a predetermined time period after a write command is inputted, in response to first and second burst signals and a write signal including a pulse generated in response to the write command. The clock enable signal generation unit is configured to generate a clock enable signal, which is enabled during a write operation period, in response to the first write signal and the first write enable signal.

Abstract translation: 提出了一种时钟控制电路，用于减少不必要的电流消耗。 时钟控制电路包括写使能信号生成单元和时钟使能信号生成单元。 写入使能信号生成单元被配置为响应于第一和第二突发信号而生成第一写入使能信号，该第一写入使能信号在写入命令被输入之后的预定时间段期间被使能，并且写入信号包括响应于 写命令。 时钟使能信号生成单元被配置为响应于第一写入信号和第一写入使能信号而生成在写入操作期间使能的时钟使能信号。

公开(公告)号：US08304215B2

公开(公告)日：2012-11-06

申请号：US13038926

申请日：2011-03-02

Applicant: Jong-Seong Kim ,  Woo-jae Lee ,  Nam-Seok Roh ,  Sang-IL Kim ,  Min-Ho Yoon ,  Young Tak Song ,  Tae Jin Kang ,  Suk Heung Oh ,  Seung-Jae Lee ,  Hye Jin Kim ,  Jin Ju Yu ,  Dong Hyun Yu ,  Young Sik Yoon ,  Jong Hwan Lee

Inventor： Jong-Seong Kim ,  Woo-jae Lee ,  Nam-Seok Roh ,  Sang-IL Kim ,  Min-Ho Yoon ,  Young Tak Song ,  Tae Jin Kang ,  Suk Heung Oh ,  Seung-Jae Lee ,  Hye Jin Kim ,  Jin Ju Yu ,  Dong Hyun Yu ,  Young Sik Yoon ,  Jong Hwan Lee

IPC: C12P19/04 ,  C12N1/20

CPC classification number: C08L1/02 ,  C12N1/20 ,  C12P19/04

Abstract: Disclosed herein is a novel gluconacetobacter strain having cellulose producing activity. Specifically, the present invention relates to a novel gluconacetobacter strain producing nano-structured cellulose in a highly efficient manner. The cellulose produced by the strain, due to its superb thermodynamic properties, can be characterized as nano-structured bacterial cellulose and therefore utilized as a bio-nano-fiber. Particularly, the cellulose can be impregnated with a resin to form a cellulose-based resin which can be effectively adapted for a substrate for a liquid crystal display (LCD).

Abstract translation: 本文公开了具有纤维素生产活性的新颖的葡萄糖酸菌属菌株。 具体地说，本发明涉及以高效的方式生产纳米结构纤维素的新颖的葡糖酸菌属菌株。 该菌株由于其极好的热力学性质而产生的纤维素可以表征为纳米结构的细菌纤维素，因此用作生物纳米纤维。 特别地，纤维素可以用树脂浸渍以形成可以有效地适用于液晶显示器（LCD）的基板的纤维素类树脂。

公开(公告)号：US20120169380A1

公开(公告)日：2012-07-05

申请号：US13243351

申请日：2011-09-23

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: H03K3/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  H03K19/018521 ,  H03K19/018585

Abstract: A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.

Abstract translation: 半导体集成电路包括：第一输出驱动器，被配置为驱动第一比较信号，该第一比较信号是通过将耦合到外部电阻器的焊盘的电压与上限参考电压进行比较而产生的，根据由上拉代码确定的驱动能力 和下拉代码，并将驱动信号作为第一输出数据输出; 以及第二输出驱动器，被配置为根据由所述上拉代码和所述下拉码确定的驾驶性能来驱动通过将所述垫的电压与下限参考电压进行比较而产生的第二比较信号，以及 输出驱动信号作为第二输出数据。

公开(公告)号：US07990784B2

公开(公告)日：2011-08-02

申请号：US12156859

申请日：2008-06-05

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C17/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2254 ,  H03K5/131

Abstract: A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.

Abstract translation: 描述了具有时钟信号发生电路的半导体存储器件，该时钟信号产生电路能够通过基于熔丝切断来控制上升和下降时钟信号的输出定时来控制符合PVT波动的数据输出。 时钟信号发生电路包括：熔丝单元，用于基于熔丝的熔丝切割产生第一和第二熔丝信号;控制信号产生单元，用于响应于熔丝信号产生第一和第二熔丝信号;时钟信号延迟单元， 延迟时钟信号，通过由控制信号指定的延迟部分延迟外部时钟信号;以及时钟产生单元，用于与延迟时钟信号的上升沿同步地产生第一内部时钟信号，并产生第二内部时钟信号 与延迟的时钟信号的下降沿同步。

公开(公告)号：US20110128049A1

公开(公告)日：2011-06-02

申请号：US12939614

申请日：2010-11-04

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: H03K3/00

CPC classification number: H03M9/00 ,  G11C7/1087 ,  G11C7/1096 ,  H03K3/356121 ,  H03K5/1534

Abstract: A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to generate an alignment signal in response to a transition timing of a data strobe signal. The duration signal generation unit is configured to generate a duration signal which is enabled during a predetermined duration in response to a write command. The data input clock pulse generation unit is configured to generate a data input clock pulse for transferring data to a global line in response to the alignment signal within an enable duration of the duration signal.

Abstract translation: 写驱动装置包括缓冲单元，持续时间信号生成单元和数据输入时钟脉冲生成单元。 缓冲单元被配置为响应于数据选通信号的转变定时产生对准信号。 持续时间信号生成单元被配置为产生响应于写入命令在预定持续时间期间使能的持续时间信号。 数据输入时钟脉冲生成单元被配置为响应于持续时间信号的使能持续时间内的对准信号，生成用于将数据传送到全局线的数据输入时钟脉冲。

公开(公告)号：US07952957B2

公开(公告)日：2011-05-31

申请号：US12455594

申请日：2009-06-04

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/10 ,  G11C11/4193 ,  G11C8/16

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076

Abstract: A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal and generates a read detection signal having a pulse width corresponding to a certain clock, and a read end signal generating unit which receives a first signal, the delayed clock signal and the read detection signal and generates a read end signal.

Abstract translation: 用于产生读取结束信号的电路包括时钟传送单元，其接收时钟信号，写入/读取状态信号和全部存储体预充电信号并输出​​延迟的时钟信号;读取信号检测单元，其接收读取的脉冲信号;以及 延迟的时钟信号并产生具有对应于某个时钟的脉冲宽度的读出检测信号，以及读出结束信号产生单元，其接收第一信号，延迟的时钟信号和读取的检测信号，并产生读出结束信号。