公开(公告)号：US12302557B2

公开(公告)日：2025-05-13

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US12300741B2

公开(公告)日：2025-05-13

申请号：US18178660

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chia-Cheng Tai ,  Tzu-Chan Weng ,  Yi-Wei Chiu ,  Chih Hsuan Cheng

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

公开(公告)号：US12300723B2

公开(公告)日：2025-05-13

申请号：US17704882

申请日：2022-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chien Cheng ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Bo-Rong Lin ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/66

Abstract: An integrated circuit includes a transistor having a plurality of semiconductor nanostructures arranged in a stack and corresponding to channel regions of the transistor. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide that extends downward along a side of the source/drain region.

公开(公告)号：US12300722B2

公开(公告)日：2025-05-13

申请号：US18750589

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap. A backside power rail is included.

公开(公告)号：US12300659B2

公开(公告)日：2025-05-13

申请号：US17646816

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Jui Huang ,  Chien Ling Hwang ,  Chih-Wei Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538

Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

公开(公告)号：US12300644B2

公开(公告)日：2025-05-13

申请号：US17841223

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chia-Li Lin ,  Yu-Chih Huang ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/00

Abstract: In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

公开(公告)号：US12300575B2

公开(公告)日：2025-05-13

申请号：US17661622

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chuei-Tang Wang ,  Shih-Chang Ku ,  Chien-Yuan Huang

IPC: H01L23/433 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A device includes a first semiconductor device including a first bonding layer; a second semiconductor device bonded to the first bonding layer of the first semiconductor device; thermal structures disposed beside the second semiconductor device and on the first bonding layer, wherein the thermal structures include a conductive material, wherein the thermal structures are electrically isolated from the first semiconductor device and from the second semiconductor device; an encapsulant disposed on the first bonding layer, wherein the encapsulant surrounds the second semiconductor device and surrounds the thermal structures; and a second bonding layer disposed over the encapsulant, the thermal structures, and the second semiconductor device.

公开(公告)号：US12300536B2

公开(公告)日：2025-05-13

申请号：US17477333

申请日：2021-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Jia-Chuan You ,  Li-Zhen Yu ,  Lin-Yu Huang

IPC: H01L21/768 ,  H01L23/522 ,  H10D30/62 ,  H10D62/13

Abstract: A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.

公开(公告)号：US12300487B2

公开(公告)日：2025-05-13

申请号：US16559062

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Yu Liu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/02 ,  G03F7/004 ,  G03F7/16

Abstract: A method of forming a photoresist pattern includes forming an upper layer including a floating additive polymer over a photoresist layer formed on a substrate. The photoresist layer is selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer, and the upper layer is removed. The floating additive polymer is a siloxane polymer.

公开(公告)号：US20250151317A1

公开(公告)日：2025-05-08

申请号：US19015324

申请日：2025-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Chi-Hao Chang ,  Jr-Hung Li

IPC: H10D30/62 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.