公开(公告)号：US5995415A

公开(公告)日：1999-11-30

申请号：US159142

申请日：1998-09-23

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G11C16/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C7/00

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/12

Abstract: A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

Abstract translation: 具有柔性库分隔体系结构的同时操作的非易失性存储器件包括存储器阵列20，存储器阵列20包括布置在多个列和行中的多个存储器单元，多个位线28和30，每个位线连接到相应的列 存储器单元，每个位线包括由指定上存储体和下存储体之间的存储器分区边界的间隙分隔的第一和第二位线段，以及耦合到存储器单元的各行的X解码器22进行行解码 存储器阵列响应于接收上部和下部存储器地址。 两个预解码器24和26耦合到X解码器22.两个Y解码器32和34分别耦合到位线段以对上和下存储体中的存储单元提供列解码。

公开(公告)号：US5644531A

公开(公告)日：1997-07-01

申请号：US551705

申请日：1995-11-01

Applicant: Tiao Hua Kuo ,  Chung K. Chang ,  Johnny Chen ,  James C. Y. Yu

Inventor： Tiao Hua Kuo ,  Chung K. Chang ,  Johnny Chen ,  James C. Y. Yu

IPC: G11C16/02 ,  G11C16/10 ,  G11C7/00

CPC classification number: G11C16/10

Abstract: A programming algorithm for a flash memory wherein programming circuitry is subdivided into a set of separately controllable groups. The algorithm detects a number of logic zeros to be programmed into a flash cell array by each group and switches among the groups such that a number of simultaneously programmed cells in the flash cell array does not exceed a predetermined number and such that maximum available programming current is used to enhance programming speed.

Abstract translation: 一种用于闪速存储器的编程算法，其中编程电路被细分为一组可单独控制的组。 该算法检测要由每个组编程到闪存单元阵列中的多个逻辑零，并且在组之间切换，使得闪存单元阵列中的多个同时编程的单元不超过预定数量，并且使得最大可用编程电流 用于提高编程速度。

公开(公告)号：US06662262B1

公开(公告)日：2003-12-09

申请号：US09420535

申请日：1999-10-19

Applicant: Yasushi Kasa ,  Johnny Chung-Lee Chen ,  Guowei Wang ,  Tiao-Hua Kuo

Inventor： Yasushi Kasa ,  Johnny Chung-Lee Chen ,  Guowei Wang ,  Tiao-Hua Kuo

IPC: G06F1200

CPC classification number: G11C8/12 ,  G11C15/046 ,  G11C16/22

Abstract: A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.

Abstract translation: 同时操作的闪存，能够为OTP扇区提供双重保护。 优选的同时操作闪速存储器包括OTP写保护CAM，如果OTP扇区被写保护，其处于编程状态。 此外，优选的同时闪存还包括与OTP写保护CAM电连接的OTP扇区锁CAM。 OTP扇区锁CAM用于将OTP写保护CAM锁定在编程状态，而后者又将OTP扇区指定为只读。

公开(公告)号：US6033955A

公开(公告)日：2000-03-07

申请号：US159023

申请日：1998-09-23

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G11C16/04 ,  G11C5/00 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C5/063 ,  G11C16/08 ,  G11C8/10 ,  G11C8/12

Abstract: A method of forming flexibly partitioned metal line segments 10 and 12 for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer 2 comprising a plurality of basic metal layer segments 2a, 2b, 2c, . . . 2j separated by a plurality of gaps 6a, 6b, 6c, . . . 6i, each of the gaps having a predefined gap interval length, and providing a metal option layer 8 comprising a plurality of metal option layer segments on the basic metal layer 2, the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.

Abstract translation: 在具有柔性库分隔结构的同时操作的闪速存储器件中形成用于单独存储体的柔性分隔的金属线段10和12的方法包括以下步骤：提供包括多个基本金属层段2a，2b的基本金属层2 ，2c，。 。 。 2j由多个间隙6a，6b，6c，...分开。 。 。 如图6i所示，每个间隙具有预定的间隙间隔长度，并且提供包括在基本金属层2上的多个金属可选层段的金属选择层8，金属选择层段与基本金属层段之间的间隙重叠，但是 留下一个间隙打开，以形成用于单独存储体的金属线段。

公开(公告)号：US06005803A

公开(公告)日：1999-12-21

申请号：US159342

申请日：1998-09-23

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/02 ,  G11C16/08 ,  G11C7/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A decoding circuit 54 for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder 44, a lower bank decoder 58, an upper bank decoder 56, and a plurality of flexibly partitioned conductive lines coupled between the upper and lower bank decoders 56 and 58. The flexibly partitioned conductive lines 60, 62, 64, . . . 74 provide a plurality of bank address pre-decoding bits for the X-decoder 44 to row decode the memory cells along the respective word lines in the memory array 20. The memory array 20 includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are coupled to two Y-decoders 32 and 34 which provide column decoding for the memory cells in the upper and lower memory banks.

Abstract translation: 用于具有灵活存储体分区体系结构的同时操作的非易失性存储器件的解码电路54包括X解码器44，下部存储体解码器58，上部存储体解码器56和多个柔性分隔的导线， 和下部分组解码器56和58.柔性分隔的导线60,62,64。 。 。 74提供多个用于X解码器44的存储体地址预解码位，以沿着存储器阵列20中的相应字线对存储器单元进行解码。存储器阵列20包括多个灵活分割的位线，包括第一和第二 位线段将存储器阵列分隔成上部和下部存储体。 上存储体和下存储体中的位线段耦合到两个Y解码器32和34，它们为上和下存储体中的存储单元提供列解码。

公开(公告)号：US5642311A

公开(公告)日：1997-06-24

申请号：US547494

申请日：1995-10-24

Applicant: Lee Cleveland ,  Chung Chang ,  Yuan Tang ,  Nancy Leong ,  Michael Fliesler ,  Tiao-Hua Kuo

Inventor： Lee Cleveland ,  Chung Chang ,  Yuan Tang ,  Nancy Leong ,  Michael Fliesler ,  Tiao-Hua Kuo

IPC: G11C16/34 ,  G11C7/00

CPC classification number: G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.

Abstract translation: 一种包括闪存EEPROM存储单元阵列的集成电路，其中在施加每个擦除脉冲之后提供过电压校正。

公开(公告)号：US5357458A

公开(公告)日：1994-10-18

申请号：US83736

申请日：1993-06-25

Applicant: James Yu ,  Tiao-Hua Kuo

Inventor： James Yu ,  Tiao-Hua Kuo

IPC: G11C5/14 ,  G11C15/00 ,  G11C15/04 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/76 ,  G11C15/00 ,  G11C16/30 ,  G11C29/789 ,  G11C5/143

Abstract: A system for allowing a content addressable memory (CAM) to operate with first and second power voltage levels including: a first input voltage for providing a first bias to the content addressable memory; a second input voltage for providing a second bias to the content addressable memory; and a selection device coupled to the first input voltage and the second input voltage for decoupling the first input voltage from the content addressable memory and coupling the second input voltage to the content addressable memory in response to coupling the second power voltage level to the content addressable memory. In a specific embodiment the system includes: a first power on reset coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and a second power on reset coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the content addressable memory. The system allows a CAM to operate at a power voltage level of 2.6 to 3.6 volts to reduce power dissipation and at a higher voltage during programming of an electrically programmable memory. The system provides multiple resets to a CAM for proper operation with multiple power supply levels. The system also provides a CAM that allows access to redundant addresses of an electrically programmable read only memory (EPROM) and that allows programming of the EPROM with traditional programming equipment.

Abstract translation: 一种用于允许内容可寻址存储器（CAM）以第一和第二电源电压电平工作的系统，包括：用于向内容可寻址存储器提供第一偏置的第一输入电压; 用于向所述内容可寻址存储器提供第二偏置的第二输入电压; 以及耦合到所述第一输入电压和所述第二输入电压的选择装置，用于将所述第一输入电压与所述内容可寻址存储器去耦，并且响应于将所述第二电源电压耦合到所述内容可寻址的接口，将所述第二输入电压耦合到所述内容可寻址存储器 记忆。 在具体实施例中，系统包括：第一上电复位，其耦合到内容可寻址存储器，用于当第一电源电压初始耦合到内容可寻址存储器时初始化内容可寻址存储器; 以及耦合到所述内容可寻址存储器的第二上电复位，用于当所述第二电源电压最初耦合到所述内容可寻址存储器时初始化所述内容可寻址存储器。 该系统允许CAM在2.6至3.6伏特的电源电压电平下工作，以在编程电可编程存储器期间降低功耗和更高的电压。 该系统为CAM提供多个复位，以便在多个电源电平下正常工作。 该系统还提供一个CAM，允许访问电可编程只读存储器（EPROM）的冗余地址，并允许使用传统编程设备编程EPROM。

公开(公告)号：US07443732B2

公开(公告)日：2008-10-28

申请号：US11229527

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

IPC: G11C11/34

CPC classification number: G11C5/147 ,  G11C16/12

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US20070064480A1

公开(公告)日：2007-03-22

申请号：US11229519

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/10

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源 区域和漏极区域。 该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在 第二个地区的利率要高得多。

公开(公告)号：US06470414B2

公开(公告)日：2002-10-22

申请号：US09893247

申请日：2001-06-26

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G06F1200

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

Abstract translation: 一种用于具有灵活存储区划分架构的同步操作闪速存储器件的存储体选择器电路，包括存储器边界选项，耦合以从存储器边界选项接收存储器分区指示符信号的存储体选择器编码器，以及耦合以接收 来自银行选择器编码器的存储体选择器代码。 解码器在接收到存储器地址时输出存储体选择器输出信号，以根据选择的存储器分区边界将存储器地址指向同时操作闪速存储器件中的下部存储器组或上部存储器组。