公开(公告)号：US5357458A

公开(公告)日：1994-10-18

申请号：US83736

申请日：1993-06-25

Applicant: James Yu ,  Tiao-Hua Kuo

Inventor： James Yu ,  Tiao-Hua Kuo

IPC: G11C5/14 ,  G11C15/00 ,  G11C15/04 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/76 ,  G11C15/00 ,  G11C16/30 ,  G11C29/789 ,  G11C5/143

Abstract: A system for allowing a content addressable memory (CAM) to operate with first and second power voltage levels including: a first input voltage for providing a first bias to the content addressable memory; a second input voltage for providing a second bias to the content addressable memory; and a selection device coupled to the first input voltage and the second input voltage for decoupling the first input voltage from the content addressable memory and coupling the second input voltage to the content addressable memory in response to coupling the second power voltage level to the content addressable memory. In a specific embodiment the system includes: a first power on reset coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and a second power on reset coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the content addressable memory. The system allows a CAM to operate at a power voltage level of 2.6 to 3.6 volts to reduce power dissipation and at a higher voltage during programming of an electrically programmable memory. The system provides multiple resets to a CAM for proper operation with multiple power supply levels. The system also provides a CAM that allows access to redundant addresses of an electrically programmable read only memory (EPROM) and that allows programming of the EPROM with traditional programming equipment.

Abstract translation: 一种用于允许内容可寻址存储器（CAM）以第一和第二电源电压电平工作的系统，包括：用于向内容可寻址存储器提供第一偏置的第一输入电压; 用于向所述内容可寻址存储器提供第二偏置的第二输入电压; 以及耦合到所述第一输入电压和所述第二输入电压的选择装置，用于将所述第一输入电压与所述内容可寻址存储器去耦，并且响应于将所述第二电源电压耦合到所述内容可寻址的接口，将所述第二输入电压耦合到所述内容可寻址存储器 记忆。 在具体实施例中，系统包括：第一上电复位，其耦合到内容可寻址存储器，用于当第一电源电压初始耦合到内容可寻址存储器时初始化内容可寻址存储器; 以及耦合到所述内容可寻址存储器的第二上电复位，用于当所述第二电源电压最初耦合到所述内容可寻址存储器时初始化所述内容可寻址存储器。 该系统允许CAM在2.6至3.6伏特的电源电压电平下工作，以在编程电可编程存储器期间降低功耗和更高的电压。 该系统为CAM提供多个复位，以便在多个电源电平下正常工作。 该系统还提供一个CAM，允许访问电可编程只读存储器（EPROM）的冗余地址，并允许使用传统编程设备编程EPROM。

公开(公告)号：US6125058A

公开(公告)日：2000-09-26

申请号：US421982

申请日：1999-10-19

Applicant: Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akaogi ,  Johnny C. Chen

Inventor： Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akaogi ,  Johnny C. Chen

IPC: G11C7/06 ,  G11C7/20 ,  G11C16/28 ,  G11C16/32 ,  G11C29/02 ,  G11C29/50 ,  G11C16/06 ,  G11C7/00

CPC classification number: G11C29/026 ,  G11C16/28 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C7/062 ,  G11C7/20 ,  G11C16/04 ,  G11C2216/22

Abstract: A system for optimizing the equalization pulse of a read sense amplifier is disclosed. A number of capacitor circuits are provided that can be coupled to a timing circuit in a variety of combinations. The different combinations of coupled and decoupled capacitor circuits result in different durational lengths of the equalization pulse. A testing sequence determines the optimal durational length of the equalization pulse by testing the different combinations of coupled capacitors. The optimal combination is then permanently stored in attribute cells for optimizing the equalization pulse in normal operation.

Abstract translation: 公开了一种用于优化读出放大器的均衡脉冲的系统。 提供了多个电容器电路，其可以以各种组合耦合到定时电路。 耦合和去耦合电容电路的不同组合导致均衡脉冲的不同持续时间长度。 测试序列通过测试耦合电容器的不同组合来确定均衡脉冲的最佳持续时间长度。 然后将最优组合永久存储在属性单元中，以在正常操作中优化均衡脉冲。

公开(公告)号：US6101129A

公开(公告)日：2000-08-08

申请号：US291984

申请日：1999-04-14

Applicant: Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

Inventor： Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16

Abstract: A method for fast chip erase of memory cells in a non-volatile memory array comprises the steps of providing an acceleration voltage greater than the internal pump voltage supplied by a conventional internal voltage supply pump, providing an erase write command, and performing a fast erase operation on the memory cells, comprising the step of coupling the acceleration voltage to the sources of the memory cells in a plurality of sectors simultaneously. In an embodiment, a fast preprogramming operation is performed on the memory cells prior to the step of performing the fast erase operation in the fast chip erase mode. In a further embodiment, a fast weak programming (APDE) operation is performed on the memory cells subsequent to the step of performing the fast erase operation in the fast chip erase mode. In an additional embodiment, the step of performing the fast erase operation further comprises the steps of detecting the acceleration voltage, generating an acceleration voltage indicator signal in response to the detection of the acceleration voltage, and generating a fast chip erase write command in response to the acceleration voltage indicator signal and the erase write command.

Abstract translation: 用于在非易失性存储器阵列中快速擦除存储器单元的方法包括以下步骤：提供大于由常规内部电压供应泵提供的内部泵浦电压的加速电压，提供擦除写入命令，以及执行快速擦除 包括将加速电压与多个扇区中的存储单元的源极同时耦合的步骤。 在一个实施例中，在以快速擦除擦除模式执行快速擦除操作的步骤之前，对存储器单元执行快速预编程操作。 在另一实施例中，在执行快速擦除擦除模式中的快速擦除操作的步骤之后，对存储器单元执行快速弱编程（APDE）操作。 在另外的实施例中，执行快速擦除操作的步骤还包括以下步骤：检测加速电压，响应于加速电压的检测产生加速电压指示信号，并响应于 加速电压指示信号和擦除写命令。

公开(公告)号：US06633949B2

公开(公告)日：2003-10-14

申请号：US09892431

申请日：2001-06-26

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G06F1200

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

Abstract translation: 存储体选择器编码器包括具有多个分区边界指示符终端的分区指示器电路，多列排列的多个反相器，其中每列反相器耦合到多列ROM单元的相应一列 ROM阵列和耦合到反相器的各列的多个存储体选择器代码输出。 分区边界指示符终端能够指定存储器分区边界以识别上部存储体和下部存储体。 存储体选择器编码器能够为多个预定的存储分区边界中的每一个生成识别库选择器代码。 存储体选择器编码器基于分区边界指示符终端输出存储体选择器代码的代码位。

公开(公告)号：US06275894B1

公开(公告)日：2001-08-14

申请号：US09159489

申请日：1998-09-23

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G11C1604

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option 18, a bank selector encoder 2 coupled to receive a memory partition indicator signal from the memory boundary option 18, and a bank selector decoder 3 coupled to receive a bank selector code from the bank selector encoder 2. The decoder 3, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

Abstract translation: 一种用于具有灵活存储体分区架构的同步操作闪速存储器件的存储体选择器电路包括存储器边界选项18，耦合以从存储器边界选项18接收存储器分区指示符信号的存储体选择器编码器2以及存储体选择器解码器3 耦合以从存储体选择器编码器2接收存储体选择器代码。解码器3在接收到存储器地址时输出存储体选择器输出信号，以将同时操作中的存储器地址指向下存储体或较高存储体 闪存设备，根据所选择的内存分区边界。

公开(公告)号：US5995415A

公开(公告)日：1999-11-30

申请号：US159142

申请日：1998-09-23

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G11C16/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C7/00

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/12

Abstract: A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

Abstract translation: 具有柔性库分隔体系结构的同时操作的非易失性存储器件包括存储器阵列20，存储器阵列20包括布置在多个列和行中的多个存储器单元，多个位线28和30，每个位线连接到相应的列 存储器单元，每个位线包括由指定上存储体和下存储体之间的存储器分区边界的间隙分隔的第一和第二位线段，以及耦合到存储器单元的各行的X解码器22进行行解码 存储器阵列响应于接收上部和下部存储器地址。 两个预解码器24和26耦合到X解码器22.两个Y解码器32和34分别耦合到位线段以对上和下存储体中的存储单元提供列解码。

公开(公告)号：US07433228B2

公开(公告)日：2008-10-07

申请号：US11229519

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/10

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源 区域和漏极区域。 该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在 第二个地区的利率要高得多。

公开(公告)号：US20070064464A1

公开(公告)日：2007-03-22

申请号：US11229527

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

IPC: G11C17/00

CPC classification number: G11C5/147 ,  G11C16/12

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US06571307B1

公开(公告)日：2003-05-27

申请号：US09421758

申请日：1999-10-19

Applicant: Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akagoi ,  Yasushi Kasa

Inventor： Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akagoi ,  Yasushi Kasa

IPC: G06F1300

CPC classification number: G11C16/06 ,  G11C2216/22

Abstract: A multiple purpose bus for a flash memory device that allows six sets of data signals to utilize the bus. The multiple purpose bus includes sixteen circuit lines that extend from one end of the memory device to another end of the memory device. Control signals that correspond to each set of data signals couple the sets of data signals to the circuit lines. A grounding circuit is provided that couples the circuit lines to a ground when none of the sets of data signals are utilizing the multiple purpose bus.

Abstract translation: 用于闪存设备的多用途总线，允许六组数据信号利用总线。 多用途总线包括从存储器件的一端延伸到存储器件的另一端的十六条电路线。 对应于每组数据信号的控制信号将数据信号组耦合到电路线。 当没有一组数据信号正在利用多用途总线时，提供将电路线耦合到地的接地电路。

公开(公告)号：US06550028B1

公开(公告)日：2003-04-15

申请号：US09421470

申请日：1999-10-19

Applicant: Takao Akaogi ,  Tiao-Hua Kuo ,  Fan W. Lai

Inventor： Takao Akaogi ,  Tiao-Hua Kuo ,  Fan W. Lai

IPC: G11C2900

CPC classification number: G11C29/028 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C2029/0403

Abstract: An array threshold voltage test mode for a flash memory device is disclosed. During the test mode, a test voltage is routed directly to the gates of the flash memory transistors selected by a given address. If the test voltage causes the selected transistors to change state by crossing their threshold voltage level, the change will be reflected in the data outputs of the device. By varying the test voltages and the addresses and monitoring the data outputs, the array threshold voltage distribution can be determined for the entire device.

Abstract translation: 公开了一种用于闪存器件的阵列阈值电压测试模式。 在测试模式期间，测试电压直接路由到由给定地址选择的闪存晶体管的栅极。 如果测试电压导致所选择的晶体管通过交叉其阈值电压电平来改变状态，则该变化将反映在器件的数据输出中。 通过改变测试电压和地址并监视数据输出，可以为整个器件确定阵列阈值电压分布。