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    Electric actuator and motor used therein
    11.
    发明授权
    Electric actuator and motor used therein 有权
    其中使用的电动执行器和电机

    公开(公告)号：US07339299B2

    公开(公告)日：2008-03-04

    申请号：US11410753

    申请日：2006-04-25

    Applicant: Naoto Sesita ,  Katuyuki Tanaka ,  Yusuke Mizukoshi ,  Hiroyuki Kurihara ,  Yoshihisa Watanabe ,  Kazuhito Yokomori

    Inventor： Naoto Sesita ,  Katuyuki Tanaka ,  Yusuke Mizukoshi ,  Hiroyuki Kurihara ,  Yoshihisa Watanabe ,  Kazuhito Yokomori

    IPC: H02K1/17 ,  H02K5/10 ,  H02K7/116 ,  H02K5/26 ,  E05F15/10

    CPC classification number: H02K5/10 ,  H02K5/15 ,  H02K5/24 ,  H02K7/081 ,  H02K7/1166 ,  H02K15/14 ,  H02K2213/09 ,  Y10T74/19828

    Abstract: A motor comprises a rotor fixed to a shaft and a stator comprising a permanent magnet on the inner circumferential surface of a motor casing. The shaft extends from the opening end of the motor casing and has a worm wheel in a gear casing. The end face of the gear casing has an annular projection. The motor casing has an outward flange at the opening end. When the motor casing is connected with the gear casing, an elastic O-ring is fitted between a space formed by the outer circumferential surface of the annular projection, an outer vertical seat face of the gear casing and a corner of the outward flange thereby achieving suitable alignment of the motor casing with the gear casing. The permanent magnet is made of Nd magnet which is pressingly fitted on the inner circumferential surface of the motor casing.

    Abstract translation: 电动机包括固定到轴的转子和在电机壳体的内周面上包括永磁体的定子。 轴从马达壳体的开口端延伸，并在蜗轮壳体中具有蜗轮。 齿轮箱的端面具有环形突起。 马达壳体在开口端具有向外的凸缘。 当马达壳体与齿轮箱连接时，弹性O形环装配在由环形突起的外周面形成的空间，齿轮壳体的外侧垂直座面与向外凸缘的角部之间，从而实现 电动机壳体与齿轮箱的适当对准。 永磁体由压电配合在电动机壳体的内周面上的Nd磁铁制成。

    NONVOLATILE SEMICONDUCTOR MEMORY, ITS READ METHOD AND A MEMORY CARD
    12.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY, ITS READ METHOD AND A MEMORY CARD 失效
    非易失性半导体存储器，其读取方法和存储卡

    公开(公告)号：US20080049508A1

    公开(公告)日：2008-02-28

    申请号：US11838510

    申请日：2007-08-14

    Applicant: Makoto IWAI ,  Yoshihisa Watanabe

    Inventor： Makoto IWAI ,  Yoshihisa Watanabe

    IPC: G11C16/04

    CPC classification number: G11C16/3418 ,  G11C16/3427

    Abstract: A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected to both ends of the plurality of memory cells respectively, a plurality of word lines and a plurality of bit lines which are connected to the plurality of memory cells and a data read control part wherein at least one of the memory cells is selected and when data is read from that memory cell a read pass voltage is applied to a word line which is connected to a non-selected memory cell other than the selected memory cell, and after applying the read pass voltage a voltage is applied to a control gate of the first selection transistor or the second selection transistor, and when applying the read pass voltage, the read pass voltage which is applied to the word line which is connected to at least one of the non-selected memory cells which is adjacent to the first selection transistor or the second selection transistor, is made lower than the read pass voltage which is applied to the word line which is connected to another cell of the non-selected memory cells.

    Abstract translation: 非易失性半导体存储器包括存储单元阵列，该存储单元阵列具有多个与单元串联连接的NAND单元单元，第一选择晶体管和第二选择晶体管分别连接到多个存储器的两端 分别连接到多个存储单元的多个字线和多个位线，以及数据读取控制部分，其中至少一个存储器单元被选择，并且当从该存储器单元读取数据时读取 将通过电压施加到连接到除所选存储单元之外的未选择的存储单元的字线，并且在施加读取通过电压之后，将电压施加到第一选择晶体管或第二选择晶体管的控制栅极 ，并且当应用读通过电压时，施加到连接到未选择存储器中的至少一个的字线的读通过电压 使与第一选择晶体管或第二选择晶体管相邻的单元小于施加到连接到未选择的存储单元的另一单元的字线的读通过电压。

    Inspection device for inspecting projections on the surface of parts
    14.
    发明授权
    Inspection device for inspecting projections on the surface of parts 失效
    用于检查零件表面上的突起的检查装置

    公开(公告)号：US4803871A

    公开(公告)日：1989-02-14

    申请号：US48725

    申请日：1987-05-11

    Applicant: Osamu Harada ,  Akio Kojima ,  Souhei Ikeda ,  Yoshihisa Watanabe ,  Yoshihisa Tsuji

    Inventor： Osamu Harada ,  Akio Kojima ,  Souhei Ikeda ,  Yoshihisa Watanabe ,  Yoshihisa Tsuji

    IPC: H05K13/08 ,  G01B11/24 ,  G01B5/20 ,  G01B7/16 ,  G01B7/28

    CPC classification number: H05K13/08

    Abstract: An inspection device for inspecting projections of a part which can be applied to a variety of parts having projections on the surface thereof such as leads of electronic parts having varying shapes. The inspection device includes a member having a two-dimensional surface to which projections of the part are two-dimensionally pressed at a predetermined pressure, and an arrangement for detecting a pressure distribution pattern on the surface of the member as well as a converter for converting the detected pattern to two-dimensional pattern information. Further, a memory is provided for storing a reference pattern of the projections of the part so that inspection may be effected by comparing the reference pattern with the converted two-dimensional pattern information.

    Abstract translation: 一种检查装置，用于检查能够应用于具有在其表面上具有突起的各种部件的部件的突起，例如具有不同形状的电子部件的引线。 检查装置包括具有二维表面的部件，部件的突起以预定压力被二维地按压，以及用于检测部件表面上的压力分布图案的装置以及用于转换的转换器 检测到的图案为二维图案信息。 此外，提供存储器，用于存储部件的投影的参考图案，使得可以通过将参考图案与转换的二维图案信息进行比较来进行检查。

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120032243A1

    公开(公告)日：2012-02-09

    申请号：US13052152

    申请日：2011-03-21

    Applicant: Hiroyuki KUTSUKAKE ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

    Inventor： Hiroyuki KUTSUKAKE ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

    IPC: H01L29/94

    CPC classification number: H01L27/11526 ,  H01L27/11521 ,  H01L27/11529

    Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

    Abstract translation: 根据一个实施例，半导体器件包括设置在半导体衬底中的至少一个半导体区域和包括设置在半导体区域中的多个电容器的电容器组，每个电容器包括设置在半导体区域上的电容器绝缘膜，电容器 设置在电容器绝缘膜上的电极以及设置在与电容器电极相邻的半导体区域中的至少一个扩散层。

    Semiconductor memory device capable of compensating variation with time of program voltage
    17.
    发明授权
    Semiconductor memory device capable of compensating variation with time of program voltage 失效
    能够补偿编程电压随时间变化的半导体存储器件

    公开(公告)号：US08102719B2

    公开(公告)日：2012-01-24

    申请号：US12683022

    申请日：2010-01-06

    Applicant: Yoshihisa Watanabe

    Inventor： Yoshihisa Watanabe

    IPC: G11C16/10

    CPC classification number: G11C16/3418 ,  G11C16/10

    Abstract: A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase.

    Abstract translation: 电压产生电路在写入时产生高于编程电压的第一电压，并在擦除时产生擦除电压。 第一晶体管具有电流路径和栅极，并且由电压产生电路产生的第一电压被提供给电流路径的一端和第一晶体管的栅极。 第一晶体管从其电流路径的另一端输出编程电压。 驱动晶体管的电流路径的一端连接到字线，并且具有提供有第一电压的栅极。 驱动晶体管具有提供有编程电压的电流通路的另一端。 应力施加部分在擦除时将擦除电压施加到第一晶体管的电流路径的另一端。

    Nonvolatile semiconductor memory, its read method and a memory card
    19.
    发明授权
    Nonvolatile semiconductor memory, its read method and a memory card 失效
    非易失性半导体存储器，其读取方式和存储卡

    公开(公告)号：US07903469B2

    公开(公告)日：2011-03-08

    申请号：US11838510

    申请日：2007-08-14

    Applicant: Makoto Iwai ,  Yoshihisa Watanabe

    Inventor： Makoto Iwai ,  Yoshihisa Watanabe

    IPC: G11C16/26

    CPC classification number: G11C16/3418 ,  G11C16/3427

    Abstract: A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected to both ends of the plurality of memory cells respectively, a plurality of word lines and a plurality of bit lines which are connected to the plurality of memory cells and a data read control part wherein at least one of the memory cells is selected and when data is read from that memory cell a read pass voltage is applied to a word line which is connected to a non-selected memory cell other than the selected memory cell, and after applying the read pass voltage a voltage is applied to a control gate of the first selection transistor or the second selection transistor, and when applying the read pass voltage, the read pass voltage which is applied to the word line which is connected to at least one of the non-selected memory cells which is adjacent to the first selection transistor or the second selection transistor, is made lower than the read pass voltage which is applied to the word line which is connected to another cell of the non-selected memory cells.

    Abstract translation: 非易失性半导体存储器包括存储单元阵列，该存储单元阵列具有多个与单元串联连接的NAND单元单元，第一选择晶体管和第二选择晶体管分别连接到多个存储器的两端 分别连接到多个存储单元的多个字线和多个位线，以及数据读取控制部分，其中至少一个存储器单元被选择，并且当从该存储器单元读取数据时读取 将通过电压施加到连接到除所选存储单元之外的未选择的存储单元的字线，并且在施加读取通过电压之后，将电压施加到第一选择晶体管或第二选择晶体管的控制栅极 ，并且当应用读通过电压时，施加到连接到未选择存储器中的至少一个的字线的读通过电压 使与第一选择晶体管或第二选择晶体管相邻的单元小于施加到连接到未选择的存储单元的另一单元的字线的读通过电压。

    NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD
    20.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD 失效
    非易失性半导体存储器，其读出方法和存储卡

    公开(公告)号：US20090154241A1

    公开(公告)日：2009-06-18

    申请号：US12361362

    申请日：2009-01-28

    Applicant: Makoto IWAI ,  Yoshihisa Watanabe

    Inventor： Makoto IWAI ,  Yoshihisa Watanabe

    IPC: G11C16/04 ,  G11C16/06 ,  G11C7/00

    CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

    Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

    Abstract translation: 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

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