公开(公告)号：US06885214B1

公开(公告)日：2005-04-26

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US07382028B2

公开(公告)日：2008-06-03

申请号：US11107625

申请日：2005-04-15

申请人： Tung-Heng Hsieh ,  Chien-Li Cheng ,  Yi-Shien Mor ,  Yung-Shun Chen

发明人： Tung-Heng Hsieh ,  Chien-Li Cheng ,  Yi-Shien Mor ,  Yung-Shun Chen

IPC分类号： H01L29/423

CPC分类号： H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.

摘要翻译： 一种形成硅化物的方法和由此形成的半导体器件。 将含Si的多晶区域转变为非晶区域，并退火以形成具有增加的晶粒尺寸的再生长多晶区域。 通过金属和具有增加的晶粒尺寸的再结晶多晶区域的反应形成硅化物层。

公开(公告)号：USD965406S1

公开(公告)日：2022-10-04

申请号：US29771462

申请日：2021-02-23

申请人： MING SHIN TOOLS CO., LTD. ,  Yung-Shun Chen ,  Cheng-Chou Wu

设计人： Yung-Shun Chen ,  Cheng-Chou Wu

公开(公告)号：US20220184826A1

公开(公告)日：2022-06-16

申请号：US17117725

申请日：2020-12-10

申请人： Yung-Shun Chen ,  Cheng-Chou Wu ,  Ming Shin Tools Co., Ltd.

发明人： YUNG-SHUN CHEN ,  CHENG-CHOU WU

IPC分类号： B26B5/00 ,  B25G1/08

摘要： A utility knife is provided, including: a housing, defining an operation compartment and a storage compartment; a blade holder, movably received within the operation compartment; a blade storing carrier, movably received within the storage compartment, including a receiving portion for receiving at least one spare blade and a grip portion; and a locking mechanism, including a base body, a movable member, a first engaging member and a second engaging member, the base body being disposed to the housing, the movable member being attached to the base body and movable between a locking position and a release position, the first engaging member being disposed on and movable with the movable member, the first engaging member and the second engaging member are releasably engaged with each other so that the blade storing carrier is detachable from the housing.

公开(公告)号：US20100177993A1

公开(公告)日：2010-07-15

申请号：US12654731

申请日：2009-12-30

申请人： Yung-Shun Chen

发明人： Yung-Shun Chen

IPC分类号： B65D33/00 ,  B65D33/16

CPC分类号： B65D75/5805 ,  B65D33/2533 ,  B65D2203/10

摘要： A packaging bag includes a sealed bag and a radio frequency identification (RFID) tag attached to an easily tearable line proximate to a sealed end of the sealed bag, such that when a user tears the sealed bag along the easily tearable line, the RFID tag is damaged to effectively prevent confidential information stored in the RFID tag from being stolen by others.

摘要翻译： 包装袋包括密封袋和附接到密封袋密封端的容易撕裂线的射频识别（RFID）标签，使得当使用者沿着容易撕裂的线撕裂密封袋时，RFID标签 被损坏以有效地防止存储在RFID标签中的机密信息被其他人窃取。

公开(公告)号：US20100177991A1

公开(公告)日：2010-07-15

申请号：US12654729

申请日：2009-12-30

申请人： Yung-Shun Chen

发明人： Yung-Shun Chen

IPC分类号： B65D30/08 ,  B32B3/30

CPC分类号： B32B15/08 ,  B32B3/02 ,  B32B3/08 ,  B32B15/20 ,  B32B27/36 ,  B32B2307/31 ,  B32B2307/4023 ,  B32B2307/41 ,  B32B2307/412 ,  B32B2307/414 ,  B32B2307/75 ,  B32B2439/00 ,  B32B2439/70 ,  B32B2439/80 ,  B32B2451/00 ,  B65D2203/10 ,  Y10T428/24612

摘要： The present invention is to provide a packaging material having a radio frequency identification (RFID) function and a bag structure using the same, wherein the packaging material comprises a surface material having an inner surface covered with a metal layer (such as aluminum foil), the metal layer has a slot with a width considerably smaller than a length thereof, and two longer side edges of the slot are connected to two feed-in ends of a radio frequency identification (RFID) chip, respectively, so as to form a slot antenna on the metal layer and enable the RFID chip to receive signals of electro-magnetic waves through the slot antenna. Therefore, the packaging material having the RFID function can be easily and speedily manufactured by forming the slot on the metal layer and installing the RFID chip to the corresponding positions of the metal layer.

摘要翻译： 本发明提供具有射频识别（RFID）功能的包装材料和使用其的袋结构，其中包装材料包括具有被金属层（例如铝箔）覆盖的内表面的表面材料， 金属层具有宽度明显小于其长度的槽，槽的两个较长侧边缘分别连接到射频识别（RFID）芯片的两个馈入端，以形成槽 金属层上的天线，并使得RFID芯片能够通过缝隙天线接收电磁波的信号。 因此，通过在金属层上形成槽并将RFID芯片安装到金属层的相应位置，可以容易且快速地制造具有RFID功能的包装材料。

公开(公告)号：US20090096609A1

公开(公告)日：2009-04-16

申请号：US12232497

申请日：2008-09-18

申请人： Chi-Fang Huang ,  Yung-Shun Chen

发明人： Chi-Fang Huang ,  Yung-Shun Chen

IPC分类号： G08B13/14 ,  B32B37/02

CPC分类号： B32B37/02 ,  B32B38/145 ,  B32B2037/243 ,  B32B2038/0092 ,  B32B2519/02 ,  G08B13/2437

摘要： The present invention discloses a packaging material with a RFID tag, and the packaging material includes a surface material, a protecting layer printed on an internal side of the surface material, a conducting layer formed on the protecting layer to constitute a pattern of a transceiver antenna, a chip coupled to a feedback terminal of the transceiver antenna to form the RFID tag, a substrate and a coupling agent for combining an internal side of the surface material with an internal side of the substrate. The invention also discloses a method of manufacturing the packaging material with the RFID tag.

摘要翻译： 本发明公开了一种具有RFID标签的包装材料，包装材料包括表面材料，印刷在表面材料的内侧的保护层，形成于保护层上的导电层，构成收发天线的图案 ，耦合到所述收发器天线的反馈端以形成所述RFID标签的芯片，用于将所述表面材料的内侧与所述衬底的内侧组合的衬底和耦合剂。 本发明还公开了一种用RFID标签制造包装材料的方法。

公开(公告)号：US20080026518A1

公开(公告)日：2008-01-31

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/8234

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US20050083075A1

公开(公告)日：2005-04-21

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US5943590A

公开(公告)日：1999-08-24

申请号：US929706

申请日：1997-09-15

申请人： Jyh-Lih Wang ,  Yung-Shun Chen

发明人： Jyh-Lih Wang ,  Yung-Shun Chen

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76229 ,  H01L21/76232 ,  Y10S148/05

摘要： A method for improving the planarity of a semiconductor chip using chemical-mechanical polishing during a shallow trench isolation process is described. Specifically, an polish-stop layer, preferably of silicon nitride, is formed over a semiconductor wafer (or optionally formed over a pad oxide layer formed on the wafer). A cap layer, preferably of polysilicon, is then formed over the polish-stop layer. The active regions of the chip are defined, preferably using a photoresist mask by photolithography. The wafer, polish-stop and cap layers are then etched, between the active regions, to form shallow trenches. A lining dielectric layer, preferably an oxide, is formed over the etched and non-etched regions to fill the shallow trenches for isolation purposes. The dielectric layer has an etching rate at least three times greater than the etching rate of cap layer. When polysilicon is selected as the cap layer and oxide is selected as the dielectric layer, the selectivity rate is greater than ten. However, the conventional oxide dielectric/nitride layer etching selectivity rate is less than three. Accordingly, the present invention provides a far greater etching selectivity rate than the prior art. In addition, the polish rate of the cap layer is much higher that that of the polish-stop layer. Therefore, the cap layer can be easily removed which reduces the CMP time while minimizing the dishing effect.

摘要翻译： 描述了在浅沟槽隔离工艺期间使用化学机械抛光改善半导体芯片的平面性的方法。 具体而言，在半导体晶片（或任选地形成在晶片上形成的焊盘氧化物层上）上形成优选氮化硅的抛光停止层。 然后在抛光停止层上形成覆盖层，优选多晶硅。 限定芯片的有源区，优选使用通过光刻法的光致抗蚀剂掩模。 然后在活性区域之间蚀刻晶片，抛光停止层和盖层，以形成浅沟槽。 在蚀刻和非蚀刻区域上形成衬里介电层，优选氧化物，以填充浅沟槽用于隔离目的。 电介质层的蚀刻速率比盖层的蚀刻速度高至少三倍。 当选择多晶硅作为覆盖层，并且选择氧化物作为电介质层时，选择率大于10。 然而，传统的氧化物介质/氮化物层蚀刻选择率小于3。 因此，本发明提供比现有技术更大的蚀刻选择速率。 此外，盖层的抛光速率比抛光停止层的抛光速率高得多。 因此，可以容易地去除盖层，这降低了CMP时间，同时最小化了凹陷效应。