公开(公告)号：US20080026518A1

公开(公告)日：2008-01-31

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/8234

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US07678655B2

公开(公告)日：2010-03-16

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US06828198B2

公开(公告)日：2004-12-07

申请号：US10392120

申请日：2003-03-19

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/28123 ,  H01L21/32139

摘要： A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

公开(公告)号：US06885214B1

公开(公告)日：2005-04-26

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US20050083075A1

公开(公告)日：2005-04-21

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US20050237841A1

公开(公告)日：2005-10-27

申请号：US10829689

申请日：2004-04-22

申请人： Shien-Yang Wu ,  Jhon-Jhy Liaw

发明人： Shien-Yang Wu ,  Jhon-Jhy Liaw

IPC分类号： G11C7/00 ,  G11C17/18

CPC分类号： G11C17/18

摘要： A programming method for fuse cells. A core circuit is applied with a first power voltage. The fuse cell includes an electrical fuse element connected to a common node, and a driver device connected between the electrical fuse element and a ground node. The ground node has a ground voltage. The fuse cell has a control gate for controlling current through the electrical fuse element. In program mode, a second power voltage is applied to the common node, a first control voltage is applied to the control gate of a selected fuse cell and a second control voltage is applied to the control gate of an unselected fuse cell. In read mode, the first power voltage is applied to the common node. The second power voltage exceeds the first power voltage. The second control voltage exceeds the ground voltage. The second control voltage is also lower than the first control voltage.

摘要翻译： 一种熔丝电池的编程方法。 核心电路采用第一电源电压。 熔丝单元包括连接到公共节点的电熔丝元件和连接在电熔丝元件和接地节点之间的驱动器件。 接地节点具有接地电压。 熔丝单元具有用于控制通过电熔丝元件的电流的控制栅极。 在编程模式下，向公共节点施加第二电源电压，将第一控制电压施加到所选择的熔丝单元的控制栅极，并且将第二控制电压施加到未选择的熔丝单元的控制栅极。 在读取模式下，第一个电源电压被施加到公共节点。 第二电源电压超过第一电源电压。 第二个控制电压超过接地电压。 第二控制电压也低于第一控制电压。

公开(公告)号：US06970394B2

公开(公告)日：2005-11-29

申请号：US10829689

申请日：2004-04-22

申请人： Shien-Yang Wu ,  Jhon-Jhy Liaw

发明人： Shien-Yang Wu ,  Jhon-Jhy Liaw

IPC分类号： G11C7/00 ,  G11C17/18

CPC分类号： G11C17/18

摘要： A programming method for fuse cells. A core circuit is applied with a first power voltage. The fuse cell includes an electrical fuse element connected to a common node, and a driver device connected between the electrical fuse element and a ground node. The ground node has a ground voltage. The fuse cell has a control gate for controlling current through the electrical fuse element. In program mode, a second power voltage is applied to the common node, a first control voltage is applied to the control gate of a selected fuse cell and a second control voltage is applied to the control gate of an unselected fuse cell. In read mode, the first power voltage is applied to the common node. The second power voltage exceeds the first power voltage. The second control voltage exceeds the ground voltage. The second control voltage is also lower than the first control voltage.

摘要翻译： 一种熔丝电池的编程方法。 核心电路采用第一电源电压。 熔丝单元包括连接到公共节点的电熔丝元件和连接在电熔丝元件和接地节点之间的驱动器件。 接地节点具有接地电压。 熔丝单元具有用于控制通过电熔丝元件的电流的控制栅极。 在编程模式下，向公共节点施加第二电源电压，将第一控制电压施加到所选择的熔丝单元的控制栅极，并且将第二控制电压施加到未选择的熔丝单元的控制栅极。 在读取模式下，第一个电源电压被施加到公共节点。 第二电源电压超过第一电源电压。 第二个控制电压超过接地电压。 第二控制电压也低于第一控制电压。

公开(公告)号：US08629050B2

公开(公告)日：2014-01-14

申请号：US13443550

申请日：2012-04-10

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry-Hak-Lay Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry-Hak-Lay Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/02

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US20080238453A1

公开(公告)日：2008-10-02

申请号：US11731444

申请日：2007-03-30

申请人： Tseng Chin Lo ,  Kuo-Tsai Li ,  Shien-Yang Wu

发明人： Tseng Chin Lo ,  Kuo-Tsai Li ,  Shien-Yang Wu

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/2891 ,  H01L2924/0002 ,  H01L2924/00

摘要： A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.

摘要翻译： 介绍了用于集成电路测试的测试线结构。 该结构包括形成在半导体衬底上的划线区域或集成电路管芯区域中的测试线焊盘阵列，形成在焊盘区域下方的多个测试设备以及选择性地连接其中一个测试设备的选择电路。 本发明的测试线结构能够通过与常规测试线上相同数量的焊盘来访问大量的测试设备，并且可以用它来进行参数，可靠性和功能测试。 采用常规集成电路测试仪中的源测量单元（SMU）来感测和强制测试设备端子上的预定测试条件，并在所选设备上进行准确的开尔文测试。 还提出了使用该测试线结构的方法。

公开(公告)号：US20070290277A1

公开(公告)日：2007-12-20

申请号：US11844161

申请日：2007-08-23

申请人： Sun-Jay Chang ,  Shien-Yang Wu

发明人： Sun-Jay Chang ,  Shien-Yang Wu

IPC分类号： H01L29/94

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7849

摘要： A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

摘要翻译： 提供一种用于制造具有由硅 - 锗组分构成的沟道区的MOSFET器件的工艺。 工艺特征采用成角度的离子注入方法，将锗离子放置在导电栅极结构下面的半导体衬底的区域中。 用作随后的高掺杂源极/漏极区域的扩散源的凸起硅形状的存在，导电栅极结构的存在以及先前位于导电栅极结构上的虚设绝缘体的去除允许成角度的注入过程放置 在半导体衬底的用于MOSFET沟道区域的部分中的锗离子。 退火程序导致在用于MOSFET沟道区的半导体衬底的部分中形成所需的硅 - 锗组分。