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    Resistance-reduced semiconductor device and methods for fabricating the same
    6.
    发明申请
    Resistance-reduced semiconductor device and methods for fabricating the same 有权
    电阻降低半导体器件及其制造方法

    公开(公告)号：US20050258499A1

    公开(公告)日：2005-11-24

    申请号：US11190913

    申请日：2005-07-28

    申请人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

    发明人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L29/06 ,  H01L29/76 ,  H01L31/062

    CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6659

    摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.

    摘要翻译： 半导体器件及其制造方法。 半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。 具有导电接触的第一介电层覆盖电阻减小的晶体管。 具有第一导电特征的第二介电层覆盖在第一介电层上。 具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。

    Method for forming integrated advanced semiconductor device using sacrificial stress layer
    7.
    发明申请
    Method for forming integrated advanced semiconductor device using sacrificial stress layer 有权
    使用牺牲应力层形成集成先进半导体器件的方法

    公开(公告)号：US20060099745A1

    公开(公告)日：2006-05-11

    申请号：US10981925

    申请日：2004-11-05

    申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

    发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

    摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

    摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

    Alternative interconnect structure for semiconductor devices
    9.
    发明授权
    Alternative interconnect structure for semiconductor devices 有权
    半导体器件的替代互连结构

    公开(公告)号：US07341935B2

    公开(公告)日：2008-03-11

    申请号：US10877103

    申请日：2004-06-25

    申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

    发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76895

    摘要： A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.

    摘要翻译： 半导体互连结构包括设置在接触表面上的有机和/或感光蚀刻缓冲层。 该结构还提供了形成在蚀刻缓冲层上的层间电介质。 用于形成互连结构的方法包括蚀刻以在层间电介质中形成开口，蚀刻操作在蚀刻缓冲层上或其上终止。 去除蚀刻缓冲层以暴露接触表面，使用可以包括湿法蚀刻，灰化或DUV曝光，随后显影的其它技术或不会导致对接触表面损坏的去除工艺。 接触表面可以是导电材料，例如硅化物，硅化物或金属合金。

    Resistance-reduced semiconductor device and methods for fabricating the same
    10.
    发明授权
    Resistance-reduced semiconductor device and methods for fabricating the same 有权
    电阻降低半导体器件及其制造方法

    公开(公告)号：US07256498B2

    公开(公告)日：2007-08-14

    申请号：US11190913

    申请日：2005-07-28

    申请人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

    发明人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

    IPC分类号： H01L27/04

    CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6659

    摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.

    摘要翻译： 半导体器件及其制造方法。 半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。 具有导电接触的第一介电层覆盖电阻减小的晶体管。 具有第一导电特征的第二介电层覆盖在第一介电层上。 具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。