公开(公告)号：US20080026518A1

公开(公告)日：2008-01-31

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/8234

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US07678655B2

公开(公告)日：2010-03-16

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US20050258499A1

公开(公告)日：2005-11-24

申请号：US11190913

申请日：2005-07-28

申请人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

发明人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L29/06 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6659

摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。 具有导电接触的第一介电层覆盖电阻减小的晶体管。 具有第一导电特征的第二介电层覆盖在第一介电层上。 具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。

公开(公告)号：US07341935B2

公开(公告)日：2008-03-11

申请号：US10877103

申请日：2004-06-25

申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76895

摘要： A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.

摘要翻译： 半导体互连结构包括设置在接触表面上的有机和/或感光蚀刻缓冲层。 该结构还提供了形成在蚀刻缓冲层上的层间电介质。 用于形成互连结构的方法包括蚀刻以在层间电介质中形成开口，蚀刻操作在蚀刻缓冲层上或其上终止。 去除蚀刻缓冲层以暴露接触表面，使用可以包括湿法蚀刻，灰化或DUV曝光，随后显影的其它技术或不会导致对接触表面损坏的去除工艺。 接触表面可以是导电材料，例如硅化物，硅化物或金属合金。

公开(公告)号：US20060099745A1

公开(公告)日：2006-05-11

申请号：US10981925

申请日：2004-11-05

申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

公开(公告)号：US20050212058A1

公开(公告)日：2005-09-29

申请号：US10806217

申请日：2004-03-23

申请人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

发明人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L29/06 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659

摘要： A resistance-reduced semiconductor device and fabrication thereof. The semiconductor device of the invention includes a semiconductor device body exposing at least one silicon-containing portion, a metal silicide layer with a first resistivity overlying the silicon-containing portion and a conductor layer with a second resistivity overlying the metal silicide layer, wherein the second resistivity is smaller than the first resistivity.

摘要翻译： 一种电阻降低半导体器件及其制造。 本发明的半导体器件包括暴露至少一个含硅部分的半导体器件本体，覆盖硅含量部分的第一电阻率的金属硅化物层和覆盖金属硅化物层的第二电阻率的导体层，其中 第二电阻率小于第一电阻率。

公开(公告)号：US07256498B2

公开(公告)日：2007-08-14

申请号：US11190913

申请日：2005-07-28

申请人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

发明人： Yi-Chun Huang ,  Jyu-Horng Shieh ,  Ju-Wang Hsu

IPC分类号： H01L27/04

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6659

摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。 具有导电接触的第一介电层覆盖电阻减小的晶体管。 具有第一导电特征的第二介电层覆盖在第一介电层上。 具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。

公开(公告)号：US07223647B2

公开(公告)日：2007-05-29

申请号：US10981925

申请日：2004-11-05

申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

公开(公告)号：US20050285268A1

公开(公告)日：2005-12-29

申请号：US10877103

申请日：2004-06-25

申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

IPC分类号： H01L21/311 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76802 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76895

摘要： A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.

摘要翻译： 半导体互连结构包括设置在接触表面上的有机和/或感光蚀刻缓冲层。 该结构还提供了形成在蚀刻缓冲层上的层间电介质。 用于形成互连结构的方法包括蚀刻以在层间电介质中形成开口，蚀刻操作在蚀刻缓冲层上或其上终止。 去除蚀刻缓冲层以暴露接触表面，使用可以包括湿法蚀刻，灰化或DUV曝光，随后显影的其它技术或不会导致对接触表面损坏的去除工艺。 接触表面可以是导电材料，例如硅化物，硅化物或金属合金。

公开(公告)号：US20070093033A1

公开(公告)日：2007-04-26

申请号：US11258469

申请日：2005-10-24

申请人： Chih-Hao Wang ,  Yen-Ping Wang ,  Steve Ting ,  Yi-Chun Huang

发明人： Chih-Hao Wang ,  Yen-Ping Wang ,  Steve Ting ,  Yi-Chun Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.

摘要翻译： 提供了一种超浅结（USJ）FET器件及其形成方法，其具有改善的对SDE或LDD掺杂区界面的控制以提高器件性能和可靠性，该方法包括提供半导体衬底; 形成栅极结构，所述栅极结构包括栅极电介质，上覆栅极电极和邻近所述栅电极的任一侧的第一偏移间隔物; 在与相应的第一偏移间隔物相邻的相应源极和漏极区域上形成包含掺杂剂的至少一个掺杂半导体层; 在相邻的第一偏移间隔物附近形成第二偏移间隔物; 并且对所述至少一个半导体层进行热处理以引起所述掺杂剂的扩散以在所述半导体衬底中形成掺杂区域。