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17 条记录 (耗时 0.036 秒)

    Spacer for semiconductor structure contact
    3.
    发明授权
    Spacer for semiconductor structure contact 有权
    用于半导体结构接触的间隔物

    公开(公告)号：US08877614B2

    公开(公告)日：2014-11-04

    申请号：US13272875

    申请日：2011-10-13

    申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

    发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/20 ,  H01L21/768 ,  H01L29/66

    CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/66636

    摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.

    摘要翻译： 一个实施例是半导体结构。 半导体结构包括外延区域，栅极结构，接触间隔物和蚀刻停止层。 外延区域在衬底中。 外延区的顶表面从衬底的顶表面升高，并且外延区具有在衬底的顶表面和外延区的顶表面之间的刻面。 栅极结构在衬底上。 接触间隔物横向在外延区域的小面和栅极结构之间。 蚀刻停止层在每个接触间隔物和外延区域的顶表面之上并相邻。 接触间隔物的蚀刻选择性与蚀刻停止层的蚀刻选择性的比率等于或小于3:1。

    Semiconductor structure and method
    4.
    发明授权
    Semiconductor structure and method 有权
    半导体结构与方法

    公开(公告)号：US08692353B2

    公开(公告)日：2014-04-08

    申请号：US13224896

    申请日：2011-09-02

    申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

    发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

    IPC分类号： H01L29/06

    CPC分类号： H01L21/76227 ,  H01L21/823437 ,  H01L27/0694 ,  H01L27/11

    摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.

    摘要翻译： 一个实施例是半导体结构。 半导体结构在衬底上包括至少两个栅极结构。 栅极结构在栅极结构之间限定凹陷，并且凹部由垂直方向上的深度限定。 深度是从至少一个栅极结构的顶表面到衬底的顶表面之下的深度，并且深度在衬底中的隔离区域中延伸。 半导体结构还包括在凹部中的填充材料。 填充材料在垂直方向上具有第一厚度。 该半导体结构还包括在凹槽中和填充材料之上的层间电介质层。 所述层间电介质层在所述至少一个栅极结构的顶表面的垂直方向上具有第二厚度。 第一厚度大于第二厚度。

    Polysilicon resistor formation in a gate-last process
    5.
    发明授权
    Polysilicon resistor formation in a gate-last process 有权
    多晶硅电阻器在栅极最后工艺中形成

    公开(公告)号：US08569141B2

    公开(公告)日：2013-10-29

    申请号：US13222181

    申请日：2011-08-31

    申请人： Chun-Hung Huang ,  Jyh-Huei Chen

    发明人： Chun-Hung Huang ,  Jyh-Huei Chen

    IPC分类号： H01L21/20

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： A method includes forming a polysilicon layer over a substrate, forming a hard mask over the polysilicon layer, and doping a first portion of the hard mask with a dopant to form a doped hard mask region, wherein a second portion of the hard mask is not doped with the dopant. An etching step is performed to etch the first and the second portions of the hard mask, wherein the second portion of the hard mask is removed, and wherein at least a bottom portion of the doped hard mask region is not removed. After the etching step, the bottom portion of the doped hard mask region is removed. Electrical connections are formed to connect to a portion of the polysilicon layer in order to form a resistor.

    摘要翻译： 一种方法包括在衬底上形成多晶硅层，在多晶硅层上形成硬掩模，以及用掺杂剂掺杂硬掩模的第一部分以形成掺杂的硬掩模区域，其中硬掩模的第二部分不是 掺杂掺杂剂。 执行蚀刻步骤来蚀刻硬掩模的第一和第二部分，其中去除硬掩模的第二部分，并且其中至少掺杂的硬掩模区域的底部部分不被去除。 在蚀刻步骤之后，去除掺杂的硬掩模区域的底部。 形成电连接以连接到多晶硅层的一部分以形成电阻器。

    SEMICONDUCTOR DEVICE WITH MULTI-FUNCTIONAL DIELECTRIC LAYER
    6.
    发明申请
    SEMICONDUCTOR DEVICE WITH MULTI-FUNCTIONAL DIELECTRIC LAYER 有权
    具有多功能电介质层的半导体器件

    公开(公告)号：US20100320465A1

    公开(公告)日：2010-12-23

    申请号：US12861642

    申请日：2010-08-23

    申请人： Jyh-Huei Chen

    发明人： Jyh-Huei Chen

    IPC分类号： H01L29/04

    CPC分类号： H01L29/7843 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/78

    摘要： A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The composite dielectric layer covers part of a semiconductor substrate that includes a gate structure. The tensile stressed nitride layer protects the oxide layer and alleviates oxide damage during a pre-silicidation PAI (pre-amorphization implant) process. Portions of the gate structure and the semiconductor substrate not covered by the composite dielectric layer include amorphous portions that include the PAI implanted dopant impurities. A silicide material is disposed on the gate structure and portions of the semiconductor substrate not covered by the composite dielectric layer.

    摘要翻译： 包括氧化物层上的拉伸应力氮化物层的复合电介质层用于作为SMT（应力记忆技术）膜的双重功能，同时执行退火操作，然后保持部分完整，因为其被图案化以进一步用作 在随后的硅化过程中的RPO膜。 复合介电层覆盖包括栅极结构的半导体衬底的一部分。 拉伸应力氮化物层保护氧化物层并减轻在预硅化PAI（非晶化前植入）过程中的氧化物损伤。 未被复合电介质层覆盖的栅极结构和半导体衬底的部分包括包含PAI注入掺杂杂质的非晶部分。 硅化物材料设置在栅极结构上，半导体衬底的未被复合电介质层覆盖的部分。

    Semiconductor Structure and Method
    7.
    发明申请
    Semiconductor Structure and Method 有权
    半导体结构与方法

    公开(公告)号：US20130056830A1

    公开(公告)日：2013-03-07

    申请号：US13224896

    申请日：2011-09-02

    申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

    发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

    IPC分类号： H01L29/78 ,  H01L21/76

    CPC分类号： H01L21/76227 ,  H01L21/823437 ,  H01L27/0694 ,  H01L27/11

    摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.

    摘要翻译： 一个实施例是半导体结构。 半导体结构在衬底上包括至少两个栅极结构。 栅极结构在栅极结构之间限定凹陷，并且凹部由垂直方向上的深度限定。 深度是从至少一个栅极结构的顶表面到衬底的顶表面之下的深度，并且深度在衬底中的隔离区域中延伸。 半导体结构还包括在凹部中的填充材料。 填充材料在垂直方向上具有第一厚度。 该半导体结构还包括在凹槽中和填充材料之上的层间电介质层。 所述层间电介质层在所述至少一个栅极结构的顶表面的垂直方向上具有第二厚度。 第一厚度大于第二厚度。

    Polysilicon Resistor Formation in a Gate-Last Process
    8.
    发明申请
    Polysilicon Resistor Formation in a Gate-Last Process 有权
    多晶硅电阻器在栅极 - 最后工艺中形成

    公开(公告)号：US20130052789A1

    公开(公告)日：2013-02-28

    申请号：US13222181

    申请日：2011-08-31

    申请人： Chun-Hung Huang ,  Jyh-Huei Chen

    发明人： Chun-Hung Huang ,  Jyh-Huei Chen

    IPC分类号： H01L21/20

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： A method includes forming a polysilicon layer over a substrate, forming a hard mask over the polysilicon layer, and doping a first portion of the hard mask with a dopant to form a doped hard mask region, wherein a second portion of the hard mask is not doped with the dopant. An etching step is performed to etch the first and the second portions of the hard mask, wherein the second portion of the hard mask is removed, and wherein at least a bottom portion of the doped hard mask region is not removed. After the etching step, the bottom portion of the doped hard mask region is removed. Electrical connections are formed to connect to a portion of the polysilicon layer in order to form a resistor.

    摘要翻译： 一种方法包括在衬底上形成多晶硅层，在多晶硅层上形成硬掩模，并用掺杂剂掺杂硬掩模的第一部分以形成掺杂的硬掩模区域，其中硬掩模的第二部分不是 掺杂掺杂剂。 执行蚀刻步骤来蚀刻硬掩模的第一和第二部分，其中去除硬掩模的第二部分，并且其中至少掺杂的硬掩模区域的底部部分不被去除。 在蚀刻步骤之后，去除掺杂的硬掩模区域的底部。 形成电连接以连接到多晶硅层的一部分以形成电阻器。

    Backside bevel protection
    9.
    发明授权
    Backside bevel protection 有权
    背面斜角保护

    公开(公告)号：US08338242B2

    公开(公告)日：2012-12-25

    申请号：US13077257

    申请日：2011-03-31

    申请人： Jung-Tzu Hsu ,  Ching-Chung Pai ,  Yu-Hsien Lin ,  Jyh-Huei Chen

    发明人： Jung-Tzu Hsu ,  Ching-Chung Pai ,  Yu-Hsien Lin ,  Jyh-Huei Chen

    IPC分类号： H01L21/338

    CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

    摘要： The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

    摘要翻译： 本公开提供了用于在替代栅极结构中去除虚设多晶硅层期间防止在衬底背面暴露多晶硅蚀刻化学物质的多晶硅层和硅衬底的方法和结构。 使用热沉积工艺或工艺沉积用于偏置间隔物和/或接触蚀刻停止层（CESL）的电介质层以覆盖衬底背面上的多晶硅层。 由于在后侧斜面处的多晶硅层的完全去除以及由此导致的硅衬底的蚀刻，这种机理减少或消除了源自衬底背面的斜面的颗粒。