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    Integrated controller for training memory physical layer interface
    14.
    发明授权
    Integrated controller for training memory physical layer interface 有权

    公开(公告)号：US09639495B2

    公开(公告)日：2017-05-02

    申请号：US14318114

    申请日：2014-06-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Glenn A. Dearth ,  Gerry Talbot ,  Anwar Kashem ,  Edoardo Prete ,  Brian Amick

    IPC: G06F12/00 ,  G06F13/40

    CPC classification number: G06F13/4072 ,  G06F13/1689

    Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

    Multi-chiplet clock delay compensation
    15.
    发明授权
    Multi-chiplet clock delay compensation 有权

    公开(公告)号：US11989050B2

    公开(公告)日：2024-05-21

    申请号：US17565382

    申请日：2021-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Deepesh John

    IPC: G06F1/08 ,  H03K5/22 ,  H03K5/00

    CPC classification number: G06F1/08 ,  H03K5/22 ,  H03K2005/00286

    Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

    MULTI-CHIPLET CLOCK DELAY COMPENSATION
    18.
    发明公开
    MULTI-CHIPLET CLOCK DELAY COMPENSATION 审中-公开

    公开(公告)号：US20230205252A1

    公开(公告)日：2023-06-29

    申请号：US17565382

    申请日：2021-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Deepesh John

    IPC: G06F1/08 ,  H03K5/22

    CPC classification number: G06F1/08 ,  H03K5/22 ,  H03K2005/00286

    Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

    Address and control signal training
    19.
    发明授权
    Address and control signal training 有权

    公开(公告)号：US09851744B2

    公开(公告)日：2017-12-26

    申请号：US14566265

    申请日：2014-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Glenn Dearth ,  Anwar Kashem ,  Sean Cummins

    IPC: G11C8/00 ,  G06F1/10 ,  G06F13/00 ,  G06F13/16 ,  G11C7/22

    CPC classification number: G06F1/10 ,  G06F13/00 ,  G06F13/1689 ,  G11C7/22

    Abstract: In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.

    ADDRESS AND CONTROL SIGNAL TRAINING
    20.
    发明申请
    ADDRESS AND CONTROL SIGNAL TRAINING 有权
    地址和控制信号训练

    公开(公告)号：US20160172013A1

    公开(公告)日：2016-06-16

    申请号：US14566265

    申请日：2014-12-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Glenn Dearth ,  Anwar Kashem ,  Sean Cummins

    IPC: G11C7/10 ,  G06F1/10

    CPC classification number: G06F1/10 ,  G06F13/00 ,  G06F13/1689 ,  G11C7/22

    Abstract: In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.

    Abstract translation: 在一种形式中，装置包括延迟电路和控制器。 延迟电路根据第一延迟信号延迟多个命令和地址信号，并向存储器接口提供延迟的命令和地址信号。 控制器执行命令和地址训练，其中控制器根据第一延迟信号提供具有第一定时的激活信号和预定地址信号，并且除了具有第二定时的预定地址信号之外的多个命令和地址信号 延迟信号，其中第二定时相对于第一定时被放宽。 控制器通过重复地向命令和地址信号提供预定命令，改变第一延迟信号以及测量从存储器接口接收到的数据信号来确定预定地址信号的定时时间。

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