公开(公告)号：US20160111625A1

公开(公告)日：2016-04-21

申请号：US14515929

申请日：2014-10-16

Applicant: Analog Devices, Inc.

Inventor： Thomas Kieran Nunan ,  Eugene Oh Hwang ,  Sunil Ashok Bhave

IPC: H01L41/047 ,  H01L41/113

CPC classification number: H01L41/047 ,  G01C19/5769 ,  H01L41/0475 ,  H01L41/0477 ,  H01L41/0478 ,  H01L41/0805 ,  H01L41/113 ,  H01L41/29 ,  H01L41/332

Abstract: A single photo mask can be used to define the three critical layers for the piezoelectric MEMS device, specifically the top electrode layer, the piezoelectric material layer, and the bottom electrode layer. Using a single photo mask removes the misalignment source caused by using multiple photo masks. Furthermore, in certain exemplary embodiments, all electrical interconnects use underpass interconnect. This simplifies the process for defining the device electrodes and the process sequence for achieving self-alignment between the piezoelectric element and the top and bottom electrodes. This self-alignment is achieved by using an oxide hard mask to etch the critical region of the top electrode, the piezoelectric material, and the bottom electrode with one mask and different etch chemistries depending on the layer being etched.

Abstract translation: 可以使用单个光掩模来定义压电MEMS器件的三个关键层，特别是顶部电极层，压电材料层和底部电极层。 使用单张照片掩模可以移除使用多张照片遮罩造成的未对准光源。 此外，在某些示例性实施例中，所有电互连使用地下通道互连。 这简化了用于限定器件电极的过程和用于实现压电元件与顶部和底部电极之间的自对准的工艺顺序。 这种自对准是通过使用氧化物硬掩模通过一个掩模蚀刻顶部电极，压电材料和底部电极的关键区域而实现的，这取决于被蚀刻的层而不同的蚀刻化学物质。

公开(公告)号：US09242856B2

公开(公告)日：2016-01-26

申请号：US14224107

申请日：2014-03-25

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

IPC: H01L23/06 ,  H01L23/34 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  B81C3/00 ,  B81C1/00

CPC classification number: B81C3/001 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/035

Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

Abstract translation: 微芯片具有基底裸片，其具有导电互连和围绕导电互连的至少一部分的隔离沟槽，以及固定到基模的帽模。 由金属材料形成的密封件位于基模和盖模之间，以将它们固定在一起。 微芯片还具有在隔离沟槽和金属密封件之间的阻挡装置，至少部分地防止金属材料与互连件接触。

公开(公告)号：US20140203422A1

公开(公告)日：2014-07-24

申请号：US14224107

申请日：2014-03-25

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

IPC: B81B7/00

CPC classification number: B81C3/001 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/035

Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

Abstract translation: 微芯片具有基底裸片，其具有导电互连和围绕导电互连的至少一部分的隔离沟槽，以及固定到基模的帽模。 由金属材料形成的密封件位于基模和盖模之间，以将它们固定在一起。 微芯片还具有在隔离沟槽和金属密封件之间的阻挡装置，至少部分地防止金属材料与互连件接触。

公开(公告)号：US11097942B2

公开(公告)日：2021-08-24

申请号：US15334619

申请日：2016-10-26

Applicant: Analog Devices, Inc.

Inventor： Thomas Kieran Nunan ,  Li Chen

IPC: B81B7/00 ,  B81C1/00 ,  B81C3/00 ,  H01L21/768 ,  H01L23/48

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

公开(公告)号：US10081535B2

公开(公告)日：2018-09-25

申请号：US13926384

申请日：2013-06-25

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang ,  Jeffrey A. Gregory

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/02 ,  H01L25/065

CPC classification number: B81B7/0029 ,  B81C1/00238 ,  B81C1/00349 ,  H01L21/02126 ,  H01L25/0657 ,  H01L2224/81801 ,  H01L2924/10253 ,  H01L2924/1461

Abstract: One or more conductive shielding plates are formed in a standard ASIC wafer top metal layer, e.g., for blocking cross-talk from MEMS device structure(s) on the MEMS wafer to circuitry on the ASIC wafer when the MEMS device is capped directly by the ASIC wafer in a wafer-level chip scale package. Generally speaking, a shielding plate should be at least slightly larger than the MEMS device structure it is shielding (e.g., a movable MEMS structure such as an accelerometer proof mass or a gyroscope resonator), and the shielding plate cannot be in contact with the MEMS device structure during or after wafer bonding. Thus, a recess is formed to ensure that there is sufficient cavity space away from the top surface of the MEMS device structure. The shielding plate is electrically conductive and can be biased, e.g., to the same voltage as the opposing MEMS device structure in order to maintain zero electrostatic attraction force between the MEMS device structure and the shielding plate.

公开(公告)号：US20180111823A1

公开(公告)日：2018-04-26

申请号：US15334619

申请日：2016-10-26

Applicant: Analog Devices, Inc.

Inventor： Thomas Kieran Nunan ,  Li Chen

IPC: B81B7/00 ,  H01L21/768 ,  B81C3/00 ,  H01L23/48

CPC classification number: B81B7/0006 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/00238 ,  B81C3/001 ,  B81C2203/036 ,  B81C2203/037 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L23/481

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

公开(公告)号：US09556017B2

公开(公告)日：2017-01-31

申请号：US13926257

申请日：2013-06-25

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0051 ,  B81B3/0005 ,  B81B3/0059 ,  B81B2207/012 ,  B81C1/00976 ,  B81C2201/112 ,  B81C2203/0118

Abstract: One or more stopper features (e.g., bump structures) are formed in a standard ASIC wafer top passivation layer for preventing MEMS device stiction vertically in integrated devices having a MEMS device capped directly by an ASIC wafer. A TiN coating may be used on the stopper feature(s) for anti-stiction. An electrical potential may be applied to the TiN anti-stiction coating of one or more stopper features.

Abstract translation: 在标准ASIC晶片顶部钝化层中形成一个或多个塞子特征（例如，凸起结构），用于在具有由ASIC晶片直接覆盖的MEMS器件的集成器件中垂直地防止MEMS器件静电。 TiN涂层可用于阻塞特征以用于抗静电。 可以将电势施加到一个或多个塞子特征的TiN抗静电涂层。

公开(公告)号：US20140131850A1

公开(公告)日：2014-05-15

申请号：US13673124

申请日：2012-11-09

Applicant: ANALOG DEVICES, INC.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

IPC: B81B7/00 ,  B81C3/00

CPC classification number: B81C3/001 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/035

Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

Abstract translation: 微芯片具有基底裸片，其具有导电互连和围绕导电互连的至少一部分的隔离沟槽，以及固定到基模的帽模。 由金属材料形成的密封件位于基模和盖模之间，以将它们固定在一起。 微芯片还具有在隔离沟槽和金属密封件之间的阻挡装置，至少部分地防止金属材料与互连件接触。