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公开(公告)号：US09764946B2
公开(公告)日：2017-09-19
申请号：US14062157
申请日：2013-10-24
Applicant: Analog Devices, Inc.
Inventor： Li Chen , Thomas Kieran Nunan , Kuang L. Yang
CPC classification number: B81B7/0035 , B81B3/0094 , B81B7/0041 , B81B2201/0235 , B81B2207/012 , B81B2207/095 , B81C1/00293 , B81C3/001 , B81C2203/019
Abstract: A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap.
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2.发明申请Apparatus and Method for Forming Alignment Features for Back Side Processing of a Wafer 有权用于形成晶片背面加工的对准特征的装置和方法公开(公告)号：US20150028499A1
公开(公告)日：2015-01-29
申请号：US13948408
申请日：2013-07-23
Applicant: Analog Devices, Inc.
Inventor： Christine H. Tsau , William David Sawyer , Thomas Kieran Nunan
IPC: H01L23/544
CPC classification number: H01L23/544 , H01L21/76898 , H01L21/78 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer.
Abstract translation: 用于在晶片制造工艺中形成用于背面晶片处理的对准特征的方法包括从晶片的顶侧形成沟槽而不是完全穿过晶片; 在沟槽的表面上形成对比材料; 并且研磨晶片的底侧以在这种研磨期间使用处理晶片来暴露沟槽以处理晶片，其中衬底暴露的沟槽的对比材料提供对准基准，用于晶片的精确对准以便背面处理晶片。
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公开(公告)号：US09446948B1
公开(公告)日：2016-09-20
申请号：US14632277
申请日：2015-02-26
Applicant: Analog Devices, Inc.
Inventor： Thomas Kieran Nunan
CPC classification number: B81C1/00476 , B81B2203/0109 , B81B2203/0338
Abstract: A method of fabricating a MEMS device provides a device substrate, forms a plurality of trenches in/on the substrate, and forms a sacrificial material on the substrate (e.g., growing or depositing the sacrificial material) to form a plurality of etch channels. Each trench defines one etch channel, and each etch channel forms an interior configured to channel etchant. The method also bonds a handle substrate to the sacrificial material of the device substrate, and removes at least a portion of the sacrificial material.
Abstract translation: 制造MEMS器件的方法提供器件衬底，在衬底中/之上形成多个沟槽，并在衬底上形成牺牲材料（例如，生长或沉积牺牲材料）以形成多个蚀刻通道。 每个沟槽限定一个蚀刻通道，并且每个蚀刻通道形成配置成通道蚀刻剂的内部。 该方法还将手柄衬底结合到器件衬底的牺牲材料，并且去除牺牲材料的至少一部分。
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4.发明申请Apparatus and Method for Preventing Stiction of MEMS Devices Encapsulated by Active Circuitry 有权用于防止主动电路封装的MEMS器件的静电的装置和方法公开(公告)号：US20140374856A1
公开(公告)日：2014-12-25
申请号：US13926257
申请日：2013-06-25
Applicant: ANALOG DEVICES, INC.
Inventor： Li Chen , Thomas Kieran Nunan , Kuang L. Yang
IPC: B81B3/00 , H01L23/00 , H01L25/07 , H01L21/311
CPC classification number: B81B3/0051 , B81B3/0005 , B81B3/0059 , B81B2207/012 , B81C1/00976 , B81C2201/112 , B81C2203/0118
Abstract: One or more stopper features (e.g., bump structures) are formed in a standard ASIC wafer top passivation layer for preventing MEMS device stiction vertically in integrated devices having a MEMS device capped directly by an ASIC wafer. A TiN coating may be used on the stopper feature(s) for anti-stiction. An electrical potential may be applied to the TiN anti-stiction coating of one or more stopper features.
Abstract translation: 在标准ASIC晶片顶部钝化层中形成一个或多个塞子特征（例如，凸起结构），用于在具有由ASIC晶片直接覆盖的MEMS器件的集成器件中垂直地防止MEMS器件静电。 TiN涂层可用于阻塞特征以用于抗静电。 可以将电势施加到一个或多个塞子特征的TiN抗静电涂层。
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5.发明申请Apparatus and Method for Shielding and Biasing in MEMS Devices Encapsulated by Active Circuitry 审中-公开用于主动电路封装的MEMS器件中的屏蔽和偏置的装置和方法公开(公告)号：US20140374850A1
公开(公告)日：2014-12-25
申请号：US13926384
申请日：2013-06-25
Applicant: Analog Devices, Inc.
Inventor： Li Chen , Thomas Kieran Nunan , Kuang L. Yang , Jeffrey Gregory
CPC classification number: B81B7/0029 , B81C1/00238 , B81C1/00349 , H01L21/02126 , H01L25/0657 , H01L2224/81801 , H01L2924/10253 , H01L2924/1461
Abstract: One or more conductive shielding plates are formed in a standard ASIC wafer top metal layer, e.g., for blocking cross-talk from MEMS device structure(s) on the MEMS wafer to circuitry on the ASIC wafer when the MEMS device is capped directly by the ASIC wafer in a wafer-level chip scale package. Generally speaking, a shielding plate should be at least slightly larger than the MEMS device structure it is shielding (e.g., a movable MEMS structure such as an accelerometer proof mass or a gyroscope resonator), and the shielding plate cannot be in contact with the MEMS device structure during or after wafer bonding. Thus, a recess is formed to ensure that there is sufficient cavity space away from the top surface of the MEMS device structure. The shielding plate is electrically conductive and can be biased, e.g., to the same voltage as the opposing MEMS device structure in order to maintain zero electrostatic attraction force between the MEMS device structure and the shielding plate.
Abstract translation: 在标准ASIC晶片顶部金属层中形成一个或多个导电屏蔽板，例如，当MEMS器件直接由该芯片封装时，用于阻止从MEMS晶片上的MEMS器件结构到ASIC晶片上的电路的串扰 ASIC晶圆采用晶圆级芯片级封装。 一般来说，屏蔽板应至少稍微大于被屏蔽的MEMS器件结构（例如，可移动MEMS结构，例如加速度计质量块或陀螺仪谐振器），并且屏蔽板不能与MEMS接触 晶片接合期间或之后的器件结构。 因此，形成凹部以确保离开MEMS器件结构的顶表面有足够的空腔。 屏蔽板是导电的，并且可以被偏置，例如与相对的MEMS器件结构相同的电压，以便在MEMS器件结构和屏蔽板之间维持零静电吸引力。
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Patent Agency Ranking
公开(公告)号：US09917243B2
公开(公告)日：2018-03-13
申请号：US14515929
申请日：2014-10-16
Applicant: Analog Devices, Inc.
Inventor： Thomas Kieran Nunan , Eugene Oh Hwang , Sunil Ashok Bhave
IPC: H01L21/311 , H01L21/32 , H01L41/047 , G01C19/5769 , H01L41/29 , H01L41/332 , H01L41/113 , H01L41/08
CPC classification number: H01L41/047 , G01C19/5769 , H01L41/0475 , H01L41/0477 , H01L41/0478 , H01L41/0805 , H01L41/113 , H01L41/29 , H01L41/332
Abstract: A single photo mask can be used to define the three critical layers for the piezoelectric MEMS device, specifically the top electrode layer, the piezoelectric material layer, and the bottom electrode layer. Using a single photo mask removes the misalignment source caused by using multiple photo masks. Furthermore, in certain exemplary embodiments, all electrical interconnects use underpass interconnect. This simplifies the process for defining the device electrodes and the process sequence for achieving self-alignment between the piezoelectric element and the top and bottom electrodes. This self-alignment is achieved by using an oxide hard mask to etch the critical region of the top electrode, the piezoelectric material, and the bottom electrode with one mask and different etch chemistries depending on the layer being etched.
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7.发明授权Apparatus and method for forming alignment features for back side processing of a wafer 有权用于形成用于晶片的背面处理的对准特征的装置和方法公开(公告)号：US09105644B2
公开(公告)日：2015-08-11
申请号：US13948408
申请日：2013-07-23
Applicant: Analog Devices, Inc.
Inventor： Christine H. Tsau , William David Sawyer , Thomas Kieran Nunan
IPC: H01L21/76 , H01L23/544 , H01L21/768 , H01L21/78
CPC classification number: H01L23/544 , H01L21/76898 , H01L21/78 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer.
Abstract translation: 用于在晶片制造工艺中形成用于背面晶片处理的对准特征的方法包括从晶片的顶侧形成沟槽而不是完全穿过晶片; 在沟槽的表面上形成对比材料; 并且研磨晶片的底侧以在这种研磨期间使用处理晶片来暴露沟槽以处理晶片，其中衬底暴露的沟槽的对比材料提供对准基准，用于晶片的精确对准以便背面处理晶片。
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公开(公告)号：US20150115376A1
公开(公告)日：2015-04-30
申请号：US14062157
申请日：2013-10-24
Applicant: Analog Devices, Inc.
Inventor： Li Chen , Thomas Kieran Nunan , Kuang L. Yang
CPC classification number: B81B7/0035 , B81B3/0094 , B81B7/0041 , B81B2201/0235 , B81B2207/012 , B81B2207/095 , B81C1/00293 , B81C3/001 , B81C2203/019
Abstract: A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap.
Abstract translation: 封盖的微加工装置在第一密封室中具有可移动的微机械加工结构，并且在与第一密封室气密隔离的第二密封室中的一个或多个互连以及其顶盖面向第一密封室的阻挡层， 使得第一密封室与盖的排气隔离。
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9.发明授权公开(公告)号：US08749036B2
公开(公告)日：2014-06-10
申请号：US13673124
申请日：2012-11-09
Applicant: Analog Devices, Inc.
Inventor： Li Chen , Thomas Kieran Nunan , Kuang L. Yang
CPC classification number: B81C3/001 , B81B7/007 , B81C1/00269 , B81C2203/0109 , B81C2203/019 , B81C2203/035
Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.
Abstract translation: 微芯片具有基底裸片，其具有导电互连和围绕导电互连的至少一部分的隔离沟槽，以及固定到基模的帽模。 由金属材料形成的密封件位于基模和盖模之间，以将它们固定在一起。 微芯片还具有在隔离沟槽和金属密封件之间的阻挡装置，至少部分地防止金属材料与互连件接触。
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公开(公告)号：US20160251214A1
公开(公告)日：2016-09-01
申请号：US14632277
申请日：2015-02-26
Applicant: Analog Devices, Inc.
Inventor： Thomas Kieran Nunan
IPC: B81C1/00
CPC classification number: B81C1/00476 , B81B2203/0109 , B81B2203/0338
Abstract: A method of fabricating a MEMS device provides a device substrate, forms a plurality of trenches in/on the substrate, and forms a sacrificial material on the substrate (e.g., growing or depositing the sacrificial material) to form a plurality of etch channels. Each trench defines one etch channel, and each etch channel forms an interior configured to channel etchant. The method also bonds a handle substrate to the sacrificial material of the device substrate, and removes at least a portion of the sacrificial material.
Abstract translation: 制造MEMS器件的方法提供器件衬底，在衬底中/之上形成多个沟槽，并在衬底上形成牺牲材料（例如，生长或沉积牺牲材料）以形成多个蚀刻通道。 每个沟槽限定一个蚀刻通道，并且每个蚀刻通道形成配置成通道蚀刻剂的内部。 该方法还将手柄衬底结合到器件衬底的牺牲材料，并且去除牺牲材料的至少一部分。
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