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    Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests
    11.
    发明授权
    Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests 有权

    公开(公告)号：US11080188B1

    公开(公告)日：2021-08-03

    申请号：US15939099

    申请日：2018-03-28

    Applicant: Apple Inc.

    Inventor： Jonathan Y. Tong ,  Ronald P. Hall ,  Christopher Colletti ,  David E. Kroesche ,  James N. Hardage, Jr.

    IPC: G06F12/0815 ,  G06F12/1036 ,  G06F12/0808 ,  G06F12/1009

    Abstract: A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.

    Prediction Confirmation for Cache Subsystem
    12.
    发明申请
    Prediction Confirmation for Cache Subsystem 有权

    公开(公告)号：US20230084736A1

    公开(公告)日：2023-03-16

    申请号：US17933603

    申请日：2022-09-20

    Applicant: Apple Inc.

    Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

    IPC: G06F12/0862

    Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

    Virtual Channel Support Using Write Table
    13.
    发明申请
    Virtual Channel Support Using Write Table 有权

    公开(公告)号：US20220083369A1

    公开(公告)日：2022-03-17

    申请号：US17143149

    申请日：2021-01-06

    Applicant: Apple Inc.

    Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

    IPC: G06F9/46 ,  G06F9/50 ,  G06F9/54

    Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

    Cache for patterns of instructions with multiple forward control transfers
    15.
    发明授权
    Cache for patterns of instructions with multiple forward control transfers 有权

    公开(公告)号：US09632791B2

    公开(公告)日：2017-04-25

    申请号：US14160242

    申请日：2014-01-21

    Applicant: Apple Inc.

    Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Ronald P. Hall ,  Michael L. Karm

    IPC: G06F12/08 ,  G06F9/38 ,  G06F12/0862

    CPC classification number: G06F9/3844 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867 ,  G06F12/0862 ,  Y02D10/13

    Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

    Instruction loop buffer with tiered power savings
    16.
    发明授权
    Instruction loop buffer with tiered power savings 有权
    指令循环缓冲器，具有分层功率节省

    公开(公告)号：US09524011B2

    公开(公告)日：2016-12-20

    申请号：US14251508

    申请日：2014-04-11

    Applicant: Apple Inc.

    Inventor： Ronald P. Hall ,  Michael L. Karm ,  Ian D. Kountanis ,  David J. Williamson

    IPC: G06F1/26 ,  G06F1/32 ,  G06F9/00 ,  G06F9/30

    CPC classification number: G06F1/3234 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

    Abstract: Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).

    Abstract translation: 公开了在执行指令循环期间降低功率的技术。 处理器可以使用多种不同的功率节省模式，例如在更多数量的循环迭代之后仅仅几次循环迭代（例如2-3）和第二更深的省电模式之后的第一省电模式。 第一省电模式可以包括保持分支预测器和/或其他结构是有效的，但是第二省电模式可以包括降低分支预测器和/或其他结构的功率。 在进入用于循环执行的省电模式之前，处理器还可以使用观察模式和指令捕获模式。 在执行具有多个后向分支（例如，嵌套循环）的复杂环路时也可以实现节电模式。

    Trace Cache with Filter for Internal Control Transfer Inclusion
    17.
    发明申请
    Trace Cache with Filter for Internal Control Transfer Inclusion 有权

    公开(公告)号：US20250021333A1

    公开(公告)日：2025-01-16

    申请号：US18352323

    申请日：2023-07-14

    Applicant: Apple Inc.

    Inventor： Ilhyun Kim ,  Niket K. Choudhary ,  Muawya M. Al-Otoom ,  Pruthivi Vuyyuru ,  Ronald P. Hall

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Disclosed techniques relate to trace caches. Trace cache circuitry may identify traces that satisfy one or more criteria. Generally, internal branches of a trace should satisfy a threshold bias level in a particular direction. To achieve this goal, the processor may initially assume that branches meet the threshold, track their usefulness in the trace context over time, and prevent inclusion of branches that fall below a usefulness threshold (which indicates that those branches are not sufficiently biased). Branches that do not meet the threshold may be added to a Bloom filter, for example. Usefulness may be tracked during trace training, when valid in a trace cache, or both.

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