中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.026 seconds)

    ATOMIC LAYER ETCHING PROCESSES
    12.
    发明申请
    ATOMIC LAYER ETCHING PROCESSES 审中-公开

    公开(公告)号：US20190122902A1

    公开(公告)日：2019-04-25

    申请号：US15792252

    申请日：2017-10-24

    Applicant: Applied Materials, Inc.

    Inventor： Jungmin Ko ,  Tom Choi ,  Junghoon Kim ,  Sean Kang ,  Mang-Mang Ling

    IPC: H01L21/67 ,  H01J37/32

    CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32899 ,  H01J2237/334 ,  H01J2237/3341 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/68742

    Abstract: Processing methods may be performed to remove unwanted materials from a substrate. The methods may include forming a remote plasma of an inert precursor in a remote plasma region of a processing chamber. The methods may include forming a bias plasma of the inert precursor within a processing region of the processing chamber. The methods may include modifying a surface of an exposed material on a semiconductor substrate within the processing region of the processing chamber with plasma effluents of the inert precursor. The methods may include extinguishing the bias plasma while maintaining the remote plasma. The methods may include adding an etchant precursor to the remote plasma region to produce etchant plasma effluents. The methods may include flowing the etchant plasma effluents to the processing region of the processing chamber. The methods may also include removing the modified surface of the exposed material from the semiconductor substrate.

    Methods for barrier layer removal
    14.
    发明授权
    Methods for barrier layer removal 有权
    阻隔层去除方法

    公开(公告)号：US09514953B2

    公开(公告)日：2016-12-06

    申请号：US14541978

    申请日：2014-11-14

    Applicant: Applied Materials, Inc.

    Inventor： Chia-Ling Kao ,  Sean Kang ,  Jeremiah T. Pender ,  Srinivas D. Nemani ,  He Ren ,  Mehul Naik

    IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/768

    CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

    Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

    Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。

    Bias voltage modulation approach for SiO/SiN layer alternating etch process
    15.
    发明授权
    Bias voltage modulation approach for SiO/SiN layer alternating etch process 有权

    公开(公告)号：US12278110B2

    公开(公告)日：2025-04-15

    申请号：US17572397

    申请日：2022-01-10

    Applicant: Applied Materials, Inc.

    Inventor： Sean Kang ,  Olivier Luere ,  Kenji Takeshita ,  Sanghyuk Choi ,  Mengnan Zou ,  Zihao Ding

    IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/311

    Abstract: Embodiments of the present disclosure generally relate to a method for etching a film stack with high selectivity and low etch recipe transition periods. In one embodiment, a method for etching a film stack having stacked pairs of oxide and nitride layers is described. The method includes transferring a substrate having a film stack formed thereon into a processing chamber, providing a first bias voltage to the substrate, etching an oxide layer of the film stack while providing the first bias voltage to the substrate, providing a second bias voltage to the substrate, the second bias voltage greater than the first bias voltage, and etching a nitride layer of the film stack while providing the second bias voltage to the substrate.

    Cyclic spacer etching process with improved profile control
    16.
    发明授权
    Cyclic spacer etching process with improved profile control 有权
    循环间隔蚀刻工艺，具有改进的轮廓控制

    公开(公告)号：US09478433B1

    公开(公告)日：2016-10-25

    申请号：US14968500

    申请日：2015-12-14

    Applicant: Applied Materials, Inc.

    Inventor： Qingjun Zhou ,  Jungmin Ko ,  Tom Choi ,  Sean Kang ,  Jeremiah Pender ,  Srinivas D. Nemani ,  Ying Zhang

    IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/3213

    CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

    Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

    Abstract translation: 本文描述的实施例涉及用于图案化衬底的方法。 诸如双重图案化和四重图案化工艺的图案化工艺可以受益于本文所述的实施例，其包括对间隔材料执行惰性等离子体处理，对间隔材料的处理区域进行蚀刻工艺，并重复惰性等离子体处理 和蚀刻工艺以形成期望的间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺，并且蚀刻工艺可以是无偏的工艺。 可以控制各种加工参数，例如工艺气体比和压力，以影响所需的间隔物轮廓。

    Methods for forming a self-aligned contact via selective lateral etch
    17.
    发明授权
    Methods for forming a self-aligned contact via selective lateral etch 有权
    通过选择性侧向蚀刻形成自对准接触的方法

    公开(公告)号：US09368369B2

    公开(公告)日：2016-06-14

    申请号：US14535055

    申请日：2014-11-06

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Jungmin Ko ,  Sean Kang

    IPC: H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/31116 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76897

    Abstract: In some embodiments methods of processing a substrate include: providing a substrate having a contact structure formed on the substrate, wherein the contact structure comprises a feature defined by gate structures, a silicon nitride layer disposed on a upper surface of the gate structures and on sidewalls and a bottom of the feature, and an oxide layer disposed over the silicon nitride layer and filling the feature; etching an opening through the oxide layer to the silicon nitride layer disposed on the bottom of the opening, wherein a width of the opening is less than a width of the feature; expanding the opening in the oxide layer to form a tapered profile; exposing the substrate to ammonia and nitrogen trifluoride to form an ammonium fluoride gas that forms an ammonium hexafluorosilicate film on the oxide layer; and heating the substrate to a second temperature to sublimate the ammonium hexafluorosilicate film.

    Abstract translation: 在一些实施例中，处理衬底的方法包括：提供具有形成在衬底上的接触结构的衬底，其中接触结构包括由栅极结构限定的特征，设置在栅极结构的上表面上和侧壁上的氮化硅层 和该特征的底部，以及设置在氮化硅层上并填充该特征的氧化物层; 将通过所述氧化物层的开口蚀刻到设置在所述开口底部的所述氮化硅层，其中所述开口的宽度小于所述特征的宽度; 膨胀氧化层中的开口以形成锥形轮廓; 将基板暴露于氨和三氟化氮以形成在氧化物层上形成六氟硅酸铵膜的氟化铵气体; 并将衬底加热至第二温度以使六氟硅酸铵膜升华。

Patent Agency Ranking