公开(公告)号：US09620200B1

公开(公告)日：2017-04-11

申请号：US15081869

申请日：2016-03-26

Applicant: ARM Limited

Inventor： Sanjay Mangal ,  Gus Yeung ,  Martin Jay Kinkade ,  Rahul Mathur ,  Bal S. Sandhu ,  George McNeil Lattimore

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/11 ,  H01L27/1104

Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

公开(公告)号：US09142266B2

公开(公告)日：2015-09-22

申请号：US14083619

申请日：2013-11-19

Applicant: ARM LIMITED

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C7/22 ,  G11C5/14

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

公开(公告)号：US09111596B2

公开(公告)日：2015-08-18

申请号：US13967908

申请日：2013-08-15

Applicant: ARM Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Wang-Kun Chen ,  Gus Yeung

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/06

CPC classification number: G11C8/08 ,  G11C7/10 ,  G11C8/06

Abstract: A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

Abstract translation: 存储器件包括排列成多行比特单元和多列比特单元的位单元阵列，并且具有多个字线和多个读出通道。 控制单元被配置为控制对位单元阵列的访问，其中响应于指定存储器地址的存储器访问请求，控制单元被配置为激活所选择的字线并激活多个读出通道，并且访问行 所述阵列中的位单元存储数据字并由存储器地址寻址。 数据字由每行位单元中的多个位单元给出的多个数据位组成。 所述控制单元还被配置为响应于屏蔽信号，并且当接收到所述存储器访问请求时屏蔽信号被断言时，所述控制单元被配置为仅激活所选字线的一部分和所述多个 读出通道，使得仅访问数据字的一部分。

公开(公告)号：US20150138901A1

公开(公告)日：2015-05-21

申请号：US14083619

申请日：2013-11-19

Applicant: Arm Limited

Inventor： Andy Wangkun CHEN ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C7/12 ,  G11C8/12

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

公开(公告)号：US08645893B1

公开(公告)日：2014-02-04

申请号：US13658072

申请日：2012-10-23

Applicant: ARM Limited

Inventor： Gus Yeung ,  Martin Jay Kinkade ,  Marlin Wayne Frederick, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

Abstract translation: 公开了一种生成集成电路的布局的方法，该布局包括标准单元和由存储器编译器生成的至少一个存储器实例，以定义集成电路的存储器件。 接收指定所需存储器实例的一个或多个属性的输入数据。 内存编译器基于输入数据并使用指定的内存架构生成所需的内存实例。 提供了一个标准的细胞库。 内存编译器引用标准单元库的至少一个属性，以便生成所需的内存实例。 然后通过用从标准单元库中选择的标准单元格填充标准单元行来生成布局，以便提供集成电路所需的功能组件，并将由存储器编译器提供的所需存储器实例集成到布局中。

公开(公告)号：US20190026417A1

公开(公告)日：2019-01-24

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US10049709B2

公开(公告)日：2018-08-14

申请号：US14986215

申请日：2015-12-31

Applicant: ARM Limited

Inventor： Gus Yeung ,  Fakhruddin Ali Bohra ,  George McNeil Lattimore

IPC: G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  G11C11/413

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.

公开(公告)号：US09721624B2

公开(公告)日：2017-08-01

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus Yeung ,  Fakhruddin Ali Bohra ,  Mudit Bhargava ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

公开(公告)号：US20170117022A1

公开(公告)日：2017-04-27

申请号：US15401588

申请日：2017-01-09

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Gus Yeung ,  James Dennis Dodrill

IPC: G11C7/10 ,  G11C29/50 ,  G11C7/20

CPC classification number: G11C7/1012 ,  G11C5/141 ,  G11C8/06 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/702

Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

公开(公告)号：US20160005448A1

公开(公告)日：2016-01-07

申请号：US14857527

申请日：2015-09-17

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C8/12 ,  G11C8/18 ,  G11C7/22

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。