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    Hybrid flash architecture of successive approximation register analog to digital converter
    11.
    发明授权
    Hybrid flash architecture of successive approximation register analog to digital converter 有权

    公开(公告)号：US10574254B2

    公开(公告)日：2020-02-25

    申请号：US16173398

    申请日：2018-10-29

    Applicant: Avnera Corporation

    Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

    IPC: H03M1/46 ,  H03M1/44 ,  H03M1/10 ,  H03M1/18

    Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

    CHOPPER STABILIZED COMPARATOR FOR SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER
    13.
    发明申请
    CHOPPER STABILIZED COMPARATOR FOR SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20190173483A1

    公开(公告)日：2019-06-06

    申请号：US16174071

    申请日：2018-10-29

    Applicant: Avnera Corporation

    Inventor： Wai Lee ,  Garry N. Link ,  Jianping Wen

    IPC: H03M1/46 ,  H03M1/06 ,  H03M1/08 ,  H03M1/44

    Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

    Digitally calibrated successive approximation register analog-to-digital converter
    15.
    发明授权
    Digitally calibrated successive approximation register analog-to-digital converter 有权

    公开(公告)号：US09831887B2

    公开(公告)日：2017-11-28

    申请号：US15391573

    申请日：2016-12-27

    Applicant: Avnera Corporation

    Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

    IPC: H03M1/10 ,  H03M1/38

    CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

    DIGITALLY CALIBRATED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
    16.
    发明申请
    DIGITALLY CALIBRATED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER 有权

    公开(公告)号：US20170126240A1

    公开(公告)日：2017-05-04

    申请号：US15391573

    申请日：2016-12-27

    Applicant: Avnera Corporation

    Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

    IPC: H03M1/10 ,  H03M1/38

    CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

    Digitally calibrated successive approximation register analog-to-digital converter
    17.
    发明授权
    Digitally calibrated successive approximation register analog-to-digital converter 有权
    数字校准的逐次逼近寄存器模数转换器

    公开(公告)号：US09531400B1

    公开(公告)日：2016-12-27

    申请号：US14932798

    申请日：2015-11-04

    Applicant: AVNERA CORPORATION

    Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

    IPC: H03M1/06 ,  H03M1/40 ,  H03M1/44 ,  H03M1/46

    CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

    Abstract translation: 电路可以包括具有第一输入，第二输入和输出的电压比较器Vd; 具有顶板和底板的第一多个电容器Cp [0：n]，其中每个顶板与电压比较器Vd的第一输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第一输入电压Vinp，参考电压Vref，共模电压Vcm和地之间; 分别具有顶板和底板的第二多个电容器Cn [0：n]，其中每个顶板与电压比较器Vd的第二输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第二输入电压Vinn，参考电压Vref，共模电压Vcm和地之间; 以及与电压比较器Vd的输出耦合的逐次逼近寄存器（SAR）控制器。

    Low supply active current mirror
    19.
    发明授权
    Low supply active current mirror 有权

    公开(公告)号：US10133293B2

    公开(公告)日：2018-11-20

    申请号：US15852757

    申请日：2017-12-22

    Applicant: Avnera Corporation

    Inventor： Garry N. Link ,  Wai Lee

    IPC: G05F3/26 ,  G05F1/10 ,  G05F3/02

    Abstract: A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.

    POWER SUPPLY FOR CLASS G AMPLIFIER
    20.
    发明申请
    POWER SUPPLY FOR CLASS G AMPLIFIER 审中-公开

    公开(公告)号：US20180198430A1

    公开(公告)日：2018-07-12

    申请号：US15858101

    申请日：2017-12-29

    Applicant: Avnera Corporation

    Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

    IPC: H03G3/00 ,  H03G3/32

    CPC classification number: H03G3/004 ,  H03F1/025 ,  H03F1/305 ,  H03F3/187 ,  H03F2200/507 ,  H03F2200/511 ,  H03G3/32

    Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

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