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    Die stacking for multi-tier 3D integration
    12.
    发明授权
    Die stacking for multi-tier 3D integration 有权

    公开(公告)号：US10930621B2

    公开(公告)日：2021-02-23

    申请号：US16930761

    申请日：2020-07-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Rahul Agarwal ,  Milind S. Bhagavat

    IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

    Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

    Integrated circuit package with integrated voltage regulator
    18.
    发明授权
    Integrated circuit package with integrated voltage regulator 有权

    公开(公告)号：US11011466B2

    公开(公告)日：2021-05-18

    申请号：US16367731

    申请日：2019-03-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Chia-Hao Cheng

    IPC: H01L23/52 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS
    19.
    发明申请
    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS 有权

    公开(公告)号：US20210098441A1

    公开(公告)日：2021-04-01

    申请号：US16586309

    申请日：2019-09-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John J. Wuu ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Rahul Agarwal

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

    Semiconductor chip with reduced pitch conductive pillars
    20.
    发明授权
    Semiconductor chip with reduced pitch conductive pillars 有权

    公开(公告)号：US10943880B2

    公开(公告)日：2021-03-09

    申请号：US16414389

    申请日：2019-05-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Lei Fu

    IPC: H01L23/00

    Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

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