公开(公告)号：US20140252547A1

公开(公告)日：2014-09-11

申请号：US13790638

申请日：2013-03-08

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, Inc.

Inventor： Chien-Hua Chen ,  Meng-Jen Wang ,  Teck-Chong Lee ,  Pao-Nan Lee

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L27/12 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/17 ,  H01L2224/8112 ,  H01L2924/15311

Abstract: The present invention relates to a semiconductor device and a process for fabricating the same. In one embodiment, the semiconductor device includes a substrate and a plurality of integrated passive devices. The integrated passive devices are disposed on the substrate and include at least two capacitors which have different capacitance values.

Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 在一个实施例中，半导体器件包括衬底和多个集成无源器件。 集成无源器件设置在衬底上并且包括具有不同电容值的至少两个电容器。

公开(公告)号：US11637172B2

公开(公告)日：2023-04-25

申请号：US17083281

申请日：2020-10-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L23/14 ,  H01L23/15 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US10475718B2

公开(公告)日：2019-11-12

申请号：US15599379

申请日：2017-05-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hung-Yi Lin ,  Cheng-Yuan Kung ,  Teck-Chong Lee ,  Shiuan-Yu Lin

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/532 ,  H01L21/683 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.

公开(公告)号：US10304765B2

公开(公告)日：2019-05-28

申请号：US15618084

申请日：2017-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Ming-Hung Chen ,  Hsu-Chiang Shih

IPC: H01L23/04 ,  H01L23/498 ,  H01L21/48 ,  H05K1/16 ,  H01L23/538

Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.

公开(公告)号：US10211137B2

公开(公告)日：2019-02-19

申请号：US15618085

申请日：2017-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Sheng-Chi Hsieh ,  Cheng-Yuan Kung

IPC: H01L23/04 ,  H01L23/498 ,  H05K1/16 ,  H01L21/48 ,  H01L23/538

Abstract: A method for manufacturing a semiconductor device package includes providing a substrate having a first surface and a second surface opposite to the first surface; disposing a passive component layer on the first surface of the substrate; after disposing the passive component layer, forming at least one via in the substrate, wherein the via penetrates the substrate and the passive component layer; and disposing a conductive layer on the passive component layer and filling the via with the conductive layer.

公开(公告)号：US11545427B2

公开(公告)日：2023-01-03

申请号：US16447839

申请日：2019-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Chien-Hua Chen ,  Teck-Chong Lee ,  Hung-Yi Lin ,  Pao-Nan Lee ,  Hsin Hsiang Wang ,  Min-Tzu Hsu ,  Po-Hao Chen

IPC: H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

公开(公告)号：US10833144B2

公开(公告)日：2020-11-10

申请号：US15351265

申请日：2016-11-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L23/14 ,  H01L23/15 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US09997447B1

公开(公告)日：2018-06-12

申请号：US15618083

申请日：2017-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hung-Yi Lin ,  Sheng-Chi Hsieh

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of substantially parallel top-side metal bars, and a plurality of substantially parallel bottom-side metal bars. The first insulation layer is on the carrier and has a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes. The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode. The plurality of interconnection structures are within the through holes and formed as conductive through holes. The plurality of substantially parallel top-side metal bars are on the first surface of the first insulation layer. The plurality of substantially parallel bottom-side metal bars are on the second surface of the first insulation layer.

公开(公告)号：US09881917B2

公开(公告)日：2018-01-30

申请号：US14801730

申请日：2015-07-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Hsu-Chiang Shih ,  Sheng-Chi Hsieh ,  Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L27/10 ,  H01L23/48 ,  H01G4/30 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01G4/30 ,  H01L23/481 ,  H01L27/101 ,  H01L28/60 ,  H01L2224/18

Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.

公开(公告)号：US11502067B2

公开(公告)日：2022-11-15

申请号：US16518837

申请日：2019-07-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Cheng-Yuan Kung

IPC: H01L25/10 ,  H01L41/23 ,  H03H9/64 ,  H01L41/047 ,  H01L41/053 ,  H01L41/25 ,  H03H9/60 ,  H01L23/522

Abstract: A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.