公开(公告)号：US11063013B2

公开(公告)日：2021-07-13

申请号：US16413480

申请日：2019-05-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Han Chen ,  Hung-Yi Lin

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  G02B6/30 ,  G02B6/42

Abstract: A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die.

公开(公告)号：US11037846B2

公开(公告)日：2021-06-15

申请号：US16578088

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hsu-Chiang Shih ,  Cheng-Yuan Kung ,  Hung-Yi Lin

IPC: H01L21/56 ,  H01L23/28 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.

公开(公告)号：US11935841B2

公开(公告)日：2024-03-19

申请号：US17990645

申请日：2022-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hung-Yi Lin ,  Meng-Wei Hsieh ,  Yu-Pin Tsai

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/50 ,  H01L23/31

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

公开(公告)号：US20230326889A1

公开(公告)日：2023-10-12

申请号：US17715876

申请日：2022-04-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hung-Yi Lin ,  Cheng-Yuan Kung

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L24/08 ,  H01L25/0652 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2924/1434 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/08145 ,  H01L2924/1433 ,  H01L2924/1432 ,  H01L2224/16225

Abstract: An electronic package is provided. The electronic package includes a processing component and a memory unit. The processing component has a side including a first region and a second region distinct from the first region. The memory unit is disposed over the first region. The first region is configured to provide interconnection between the processing component and the memory unit, and the second region is configured to provide external connection.

公开(公告)号：US11769712B2

公开(公告)日：2023-09-26

申请号：US17334564

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsiao-Yen Lee ,  Hung-Yi Lin

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182

Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.

公开(公告)号：US11508668B2

公开(公告)日：2022-11-22

申请号：US17111350

申请日：2020-12-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hung-Yi Lin ,  Meng-Wei Hsieh ,  Yu-Pin Tsai

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/31

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

公开(公告)号：US11342282B2

公开(公告)日：2022-05-24

申请号：US16798170

申请日：2020-02-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Chiang Shih ,  Hung-Yi Lin ,  Meng-Wei Hsieh ,  Yu Sheng Chang ,  Hsiu-Chi Liu ,  Mark Gerber

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.

公开(公告)号：US10475718B2

公开(公告)日：2019-11-12

申请号：US15599379

申请日：2017-05-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hung-Yi Lin ,  Cheng-Yuan Kung ,  Teck-Chong Lee ,  Shiuan-Yu Lin

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/532 ,  H01L21/683 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.

公开(公告)号：US11784111B2

公开(公告)日：2023-10-10

申请号：US17334569

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hung-Yi Lin ,  Chin-Cheng Kuo ,  Wu Chou Hsu

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/16

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L25/167

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.

公开(公告)号：US10903907B1

公开(公告)日：2021-01-26

申请号：US16702209

申请日：2019-12-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Yu Lin ,  Cheng-Yuan Kung ,  Hung-Yi Lin

IPC: H04B10/00 ,  H04B10/40 ,  G02B6/42 ,  H04J14/00

Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.