公开(公告)号：US20090174021A1

公开(公告)日：2009-07-09

申请号：US12365141

申请日：2009-02-03

申请人： Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

发明人： Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

IPC分类号： H01L31/0232

CPC分类号： H01L27/1462 ,  H01L27/1463 ,  H01L31/02165

摘要： A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC comprises at least two different dielectric layers. A layer resistant to oxide etch is above a peripheral portion the multi-layer ARC. Further layers are above the layer resistant to oxide etch, and thereby above the peripheral portion the multi-layer ARC. A window extends down to the multi-layer ARC. A photodiode region is formed by a pn-junction of the first semiconductor type surface region and the second semiconductor type surface layer.

摘要翻译： 光电二极管包括在其至少一部分上具有第一半导体型表面区域的基板和形成在表面区域的一部分中的第二半导体型表面层。 多层抗反射涂层（ARC）在第二半导体型表面层上，其中多层ARC包括至少两个不同的电介质层。 耐氧化物蚀刻的层在多层ARC的外围部分之上。 另外的层在耐氧化物蚀刻层上方，并且因此在多层ARC的周边部分之上。 一个窗口向下延伸到多层ARC。 光电二极管区域由第一半导体型表面区域和第二半导体型表面层的pn结形成。

公开(公告)号：US20080315329A1

公开(公告)日：2008-12-25

申请号：US12037569

申请日：2008-02-26

申请人： MICHAEL DAVID CHURCH ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

发明人： MICHAEL DAVID CHURCH ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H01L27/0814

摘要： An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

摘要翻译： 集成电路包括并联连接的第一和第二二极管。 第一二极管具有第一击穿电压，并且在衬底的衬底的表面处具有彼此相邻的第一P型区域和第一N型区域，以形成横向二极管。 第二二极管具有小于第一击穿电压的第二击穿电压，并且在衬底中具有彼此相邻的第二P型区域和第二N型区域，以在表面下方形成横向二极管。第一和第二N型区域重叠 并且第一和第二P型区域电连接，由此第一和第二二极管是并联的。

公开(公告)号：US20060011997A1

公开(公告)日：2006-01-19

申请号：US11162861

申请日：2005-09-27

申请人： Alexander Kalnitsky ,  Alan Kramer

发明人： Alexander Kalnitsky ,  Alan Kramer

IPC分类号： H01L29/82

CPC分类号： G06F3/044 ,  G06F2203/04107 ,  G06K9/00053 ,  H01L27/0248

摘要： A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

摘要翻译： 平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。 每个感测单元包括具有不接地输入模式的放大器和未接地输出节点。 通过以下步骤为每个放大器提供对指纹图案敏感的输出到输入负反馈：（1）第一电容器板，其垂直放置在电介质层的上表面下方并连接到未接地的放大器输入节点 ，（2）第二电容器板，其垂直于电介质层的上表面放置在与第一电容器板紧密的水平空间关系上，并连接到未接地的输出节点，（3）指纹图案为未接地的指尖 要被检测到，哪个未接地的指尖被放置在与第一和第二电容器板紧密垂直空间关系的电介质层的上表面上。 通过在电介质层内放置多个接地的金属路径来空间地围绕第一和第二电容器板中的每一个来提供相对于静电电位的静电放电保护，这是通过不接地的指尖来承载的， 打扰指尖的未接地状态。

公开(公告)号：US06987871B2

公开(公告)日：2006-01-17

申请号：US10253841

申请日：2002-09-23

申请人： Alexander Kalnitsky ,  Alan Kramer

发明人： Alexander Kalnitsky ,  Alan Kramer

IPC分类号： G06K9/00

CPC分类号： G06F3/044 ,  G06F2203/04107 ,  G06K9/00053 ,  H01L27/0248

摘要： A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input node and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

摘要翻译： 平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。 每个感测单元包括具有未接地输入节点和未接地输出节点的放大器。 通过以下步骤为每个放大器提供对指纹图案敏感的输出到输入负反馈：（1）第一电容器板，其垂直放置在电介质层的上表面下方并连接到未接地的放大器输入节点 ，（2）第二电容器板，其垂直于电介质层的上表面与第一电容器板呈水平空间关系地放置，并连接到未接地的输出节点，（3）指纹图案为未接地的指尖 要被检测到，哪个未接地的指尖被放置在与第一和第二电容器板紧密垂直空间关系的电介质层的上表面上。 通过在电介质层内放置多个接地的金属路径来空间地围绕第一和第二电容器板中的每一个来提供相对于静电电位的静电放电保护，这是通过不接地的指尖来承载的， 打扰指尖的未接地状态。

公开(公告)号：US06773973B2

公开(公告)日：2004-08-10

申请号：US09928914

申请日：2001-08-13

申请人： Alexander Kalnitsky ,  Sudarsan Uppili ,  Sang Park

发明人： Alexander Kalnitsky ,  Sudarsan Uppili ,  Sang Park

IPC分类号： H01L21337

CPC分类号： H01L29/66272 ,  H01L29/7375

摘要： A polysilicon-emitter-type transistor has a substrate with a collector region, a base region on the collector region, and an oxide layer on the base region with an emitter window therein exposing part of the base region. The polysilicon emitter is formed by forming a first polysilicon layer of approximately 30 to 100 Angstroms at least within the emitter window and at least on the exposed base region. Then, an interfacial oxide layer being approximately 5 to 50 Angstroms thick is formed in an upper portion of the first polysilicon layer, for example, by exposing the first polysilicon layer to oxygen and annealing. Then, a second polysilicon layer is formed on the interfacial oxide layer. The thickness of the second polysilicon layer may be approximately 500 to 5000 Angstroms thick. Subsequent annealing diffuses dopants in the emitter more uniformly into the base region.

摘要翻译： 多晶硅 - 发射型晶体管具有集电极区域，集电极区域上的基极区域和基极区域上的发光体窗口的氧化物层的基板，其中露出基极区域的一部分。 多晶硅发射体通过至少在发射极窗内至少在暴露的基极区上形成大约30至100埃的第一多晶硅层而形成。 然后，例如通过将第一多晶硅层暴露于氧并进行退火，在第一多晶硅层的上部形成大约5至50埃厚的界面氧化物层。 然后，在界面氧化物层上形成第二多晶硅层。 第二多晶硅层的厚度可以为约500至5000埃厚。 随后的退火将发射极中的掺杂剂更均匀地扩散到基极区域中。

公开(公告)号：US06475873B1

公开(公告)日：2002-11-05

申请号：US09631581

申请日：2000-08-04

申请人： Alexander Kalnitsky ,  Robert F. Scheer ,  Joseph P. Ellul

发明人： Alexander Kalnitsky ,  Robert F. Scheer ,  Joseph P. Ellul

IPC分类号： H01L2120

CPC分类号： H01L28/24 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new and improved method of forming a thin film resistor is provided herein that overcomes many of the drawbacks of prior art methods. More specifically, the new method of forming a thin film provides for a well-controlled dielectric thickness under the thin film resistor which is useful for laser trimming purpose. The preferred thickness of the dielectric layer is an integer of a quarter wavelength of the optical energy used to laser trim the resistor. The new method also provides contacts to the thin film resistor that do not directly contact the thin film resistor so as to prevent any adverse process effects to the thin film resistor. More specifically, the method of forming a thin film resistor includes the steps of forming a pair of spaced-apart polysilicon islands over a semiconductor substrate, forming a dielectric layer over and between the polysilicon islands, forming contact holes through the dielectric layer to expose respective first regions of the polysilicon islands, forming a layer of thin film resistive material that extends between respective first regions of the polysilicon islands, forming another dielectric layer over the polysilicon islands and over the thin film resistive material layer, and forming metal contacts through the second dielectric layer in a manner that they make contact to respective second regions of the polysilicon islands, wherein the first and second regions of the polysilicon islands are different.

摘要翻译： 本文提供了一种新的和改进的形成薄膜电阻器的方法，其克服了现有技术方法的许多缺点。 更具体地，形成薄膜的新方法提供了薄膜电阻下的良好控制的电介质厚度，其对于激光修整目的是有用的。 电介质层的优选厚度是用于激光修整电阻器的光能的四分之一波长的整数。 该新方法还提供了不直接接触薄膜电阻器的薄膜电阻器的接触，以防止对薄膜电阻器的任何不利的处理效果。 更具体地，形成薄膜电阻器的方法包括以下步骤：在半导体衬底上形成一对间隔开的多晶硅岛，在多晶硅岛之上和之间形成电介质层，形成通过电介质层的接触孔，以暴露出相应的 形成多晶硅岛的第一区域，形成薄膜电阻材料层，其在多晶硅岛的相应的第一区之间延伸，在多晶硅岛上方和薄膜电阻材料层上方形成另一介电层，并通过第二区形成金属接触 电介质层，使得它们与多晶硅岛的相应第二区接触，其中多晶硅岛的第一和第二区不同。

公开(公告)号：US06420217B1

公开(公告)日：2002-07-16

申请号：US09632375

申请日：2000-08-03

申请人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

IPC分类号： H01L2182

CPC分类号： H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse. The transistor includes: a well region in a substrate, the well region forming the drain of the transistor; an insulating trench in the well; and a polysilicon gate extending over a portion of the substrate, a portion of the well and a portion of the trench, wherein upon reverse-biasing the junction between the well and the substrate a depletion region is formed which encompasses at least the entire portion of the surface region of the well over which the polysilicon extends.

摘要翻译： 集成的熔丝元件能够被编程为低电压工艺技术中的高电阻。 熔丝包括未掺杂的多晶硅层和硅化物层的堆叠。 施加在堆叠上的电压增加直到发生第一附聚事件，由此在硅化物层中形成不连续性。 电流进一步增加以引起第二聚集事件，从而增加不连续性的大小。 每个附聚事件会增加保险丝的电阻。 能够保持高电压的延伸漏极MOS晶体管与保险丝串联连接，以对熔丝进行编程。 晶体管包括：衬底中的阱区，形成晶体管的漏极的阱区; 井中的绝缘沟槽; 以及在所述衬底的一部分上延伸的多晶硅栅极，所述阱的一部分和所述沟槽的一部分，其中在反向偏置所述阱和所述衬底之间的结点时，形成耗尽区，所述耗尽区至少包括 多晶硅延伸的阱的表面区域。

公开(公告)号：US06271560B1

公开(公告)日：2001-08-07

申请号：US09393617

申请日：1999-09-10

申请人： Alexander Kalnitsky ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Albert Bergemont

IPC分类号： H01L29788

CPC分类号： H01L27/11519 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C2216/10 ,  H01L27/115 ,  H01L29/7887

摘要： The Frohmann-Bentchkowsky EPROM cell is programmed by utilizing biasing voltages which are sufficient to induce hot punchthrough holes to flow from the source region to the drain region, and insufficient to induce avalanche breakdown at the drain-to-semiconductor material junction. In addition, the Frohmann-Bentchkowsky EPROM cell is programmable with CMOS compatible voltages by forming the physical floating gate length of the cell to be less than the minimum physical gate length of the CMOS devices.

摘要翻译： 通过利用足以引起热穿透孔从源极区域流到漏极区域的偏置电压来编程Frohmann-Bentchkowsky EPROM单元，并且不足以在漏极 - 半导体材料结点处引起雪崩击穿。 此外，Frohmann-Bentchkowsky EPROM单元可通过将单元的物理浮置栅极长度小于CMOS器件的最小物理栅极长度来编程CMOS兼容电压。

公开(公告)号：US06218688B1

公开(公告)日：2001-04-17

申请号：US09280888

申请日：1999-03-29

申请人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

IPC分类号： H01L27095

CPC分类号： H01L27/0811

摘要： The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.

摘要翻译： 在本发明中，通过形成肖特基二极管通过场氧化物隔离区域，由常规肖特基二极管消耗的硅壳体减少。 通过场氧化物隔离区域的蚀刻需要额外的蚀刻时间，其通过常规蚀刻步骤提供，其通常在接触形成期间指定50-100％的过蚀刻。

公开(公告)号：US6141246A

公开(公告)日：2000-10-31

申请号：US373791

申请日：1999-08-13

申请人： Itai Derman ,  Moshe Meyassed ,  Alexander Kalnitsky

发明人： Itai Derman ,  Moshe Meyassed ,  Alexander Kalnitsky

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/7887 ,  G11C2216/10 ,  G11C7/06

摘要： The logic state stored in a memory cell having a Frohmann-Bentchkowsky p-channel memory transistor and a n-channel MOS access transistor is read by a sense amplifier which senses the magnitude of the current output from the memory cell during a read operation. The sense amplifier controls the voltage drop across the memory transistor and the access transistor (and a switching transistor) which, in turn, allows the difference in the magnitudes of the current from the programmed and unprogrammed cells to be optimized.

摘要翻译： 存储在具有Frohmann-Bentchkowsky p沟道存储晶体管和n沟道MOS存取晶体管的存储单元中的逻辑状态由读出放大器读出，该读出放大器在读取操作期间感测从存储单元输出的电流的大小。 读出放大器控制存储晶体管和存取晶体管（以及开关晶体管）两端的电压降，这进而使来自编程和未编程的单元的电流的幅度差被优化。