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公开(公告)号：US20170276705A1
公开(公告)日：2017-09-28
申请号：US15079364
申请日：2016-03-24
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Zhao Wang , Ajay Bhatia
Abstract: An apparatus for detecting a change in a voltage level of a power supply is disclosed. An inverter coupled to a first power supply may generate a signal dependent upon a voltage level of a second power supply. A latch coupled to the first power supply may be set based on a first voltage level of the second power supply and a first value of the signal, and re-set based on a second voltage level of the second power supply and a second value of the signal different than the first value of the signal.
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公开(公告)号：US20220231673A1
公开(公告)日：2022-07-21
申请号：US17150888
申请日：2021-01-15
Applicant: Apple Inc.
Inventor： Qi Ye , Ajay Bhatia , Vivekanandan Venugopal
IPC: H03K3/037 , H03K3/012 , H03K3/356 , H03K3/3562
Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.
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公开(公告)号：US20220156045A1
公开(公告)日：2022-05-19
申请号：US16953093
申请日：2020-11-19
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Bharan Giridhar , Mohamed H. Abu-Rahma , Ajay Bhatia , Mayur V. Joshi , Yildiz Sinangil , Aravind Kandala
Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.
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公开(公告)号：US11139803B1
公开(公告)日：2021-10-05
申请号：US17030163
申请日：2020-09-23
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia
IPC: H03K3/037 , H03K5/135 , H03K3/0233 , H03K3/3562 , H03K3/289
Abstract: Systems, apparatuses, and methods for implementing low-power flip-flops with balanced clock-to-Q delay are described. A flip-flop includes a primary latch, an upper secondary latch, and a lower secondary latch. The primary latch transmits a data value from an input port to a first node when transparent. The upper secondary latch pulls up a second node when transparent and when the first node is equal to a first value. The second node is a prebuffered data output of the flip-flop. The lower secondary latch pulls down the second node when transparent and when the first node is equal to a second value different from the first value. To ensure the flip-flop has a balanced clock-to-Q delay, a first set of clock signals coupled to transistor gates of the primary latch are delayed with respect to a second set of clock signals coupled to transistor gates of the upper secondary latch.
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公开(公告)号：US10581412B1
公开(公告)日：2020-03-03
申请号：US16369072
申请日：2019-03-29
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia , Wenhao Li
IPC: H03K3/037 , H03K19/0185
Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.
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Patent Agency Ranking
公开(公告)号：US20150228312A1
公开(公告)日：2015-08-13
申请号：US14296066
申请日：2014-06-04
Applicant: Apple Inc.
Inventor： Ajay Bhatia , Michael Dreesen
IPC: G11C5/14
CPC classification number: G06F1/3203 , G06F12/0223 , G06F12/06 , G06F2212/1016 , G11C5/14 , G11C5/147 , G11C7/1096 , G11C11/419
Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.
Abstract translation: 公开了一种系统，电压调节器和用于调节功率的方法，其中系统可以包括处理器，电压调节器电路和存储器单元。 电压调节器电路可以被配置为产生提供给存储器单元的第一电源电压。 电压调节器电路还可以被配置为根据第一电源电压的电平和参考电压的电平来调整两个输出节点的电压电平。 电压调节器电路还可以被配置为根据两个输出电压中的至少一个的电平来调节第一电源信号的电平。 电压调节电路还可以经由阻抗将第一输出电压提供给第二输出电压。
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公开(公告)号：US20150227456A1
公开(公告)日：2015-08-13
申请号：US14295997
申请日：2014-06-04
Applicant: Apple Inc.
Inventor： Ajay Bhatia , Michael Dreesen
IPC: G06F12/02
CPC classification number: G06F1/3203 , G06F12/0223 , G06F12/06 , G06F2212/1016 , G11C5/14 , G11C5/147 , G11C7/1096 , G11C11/419
Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.
Abstract translation: 用于将数据存储在存储器中的系统可以包括可以接收地址，命令和数据的电路。 电路还可以确定命令的类型，并根据该类型生成读控制或写控制信号。 该系统还可以包括多个子阵列和感测放大器。 每个子阵列可以包括多个存储单元。 每个读出放大器可以耦合到多个子阵列中的相应一个子阵列，并且可以读取存储在包括在相应子阵列中的第一存储单元中的数据。 该系统还可以包括一个或多个写入驱动器电路。 第一写入驱动器电路可以耦合到多个子阵列中的至少两个。 第一写入驱动器电路可以被配置为将数据存储在至少两个子阵列之一中的第二存储器单元中。
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公开(公告)号：US20150227186A1
公开(公告)日：2015-08-13
申请号：US14269841
申请日：2014-05-05
Applicant: Apple Inc.
Inventor： Ajay Bhatia , Michael Dreesen
CPC classification number: G06F1/3203 , G06F12/0223 , G06F12/06 , G06F2212/1016 , G11C5/14 , G11C5/147 , G11C7/1096 , G11C11/419
Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.
Abstract translation: 一种用于管理存储器中的电力的系统和方法，其中所述系统可以包括处理器和耦合到所述处理器的存储器单元。 存储单元可以将地址解码器初始化为第一功率模式。 响应于接收到与存储器单元内的位置相对应的命令和地址，存储器单元可以使用地址解码器的第一级来解码地址的至少一部分。 存储器单元还可以将地址解码器的第二级的选定部分从第一功率模式切换到第二功率模式，其中地址解码器的第二级的选择部分取决于第一级的第一级的输出信号 地址解码器的阶段。
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19.发明授权公开(公告)号：US08885393B2
公开(公告)日：2014-11-11
申请号：US13717870
申请日：2012-12-18
Applicant: Apple Inc.
Inventor： Ajay Bhatia , Hang Huang
CPC classification number: G11C5/147 , G11C7/00 , G11C11/00 , G11C11/417
Abstract: A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.
Abstract translation: 用于存储器阵列的电压源控制器包括耦合到电压源的输入端，耦合到存储器阵列的一个或多个存储器单元的输出，其中输出被配置为向存储器单元提供单元源电压。 控制器还包括一个开关电路，其被配置为：接收保持使能信号，写辅助使能信号和标准模式使能信号; 并且基于保持使能信号，写入辅助使能信号和标准模式使能信号，选择性地将一个或多个存储器单元的单元电源电压设置为以下之一：保持电压，写入辅助电压或标准模式 电压，其中保持电压和写入辅助电压小于标准模式电压。
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公开(公告)号：US11579642B2
公开(公告)日：2023-02-14
申请号：US17411491
申请日：2021-08-25
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia
IPC: G05F1/46 , G01R21/133 , G04F10/00
Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.
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