公开(公告)号：US09460920B1

公开(公告)日：2016-10-04

申请号：US14755099

申请日：2015-06-30

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Benjamin Colombeau ,  Michael Chudzik

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/42392 ,  H01L29/66742

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离的方法和装置。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 不同的材料可以是含硅材料和一种或多种III / V材料。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。

公开(公告)号：US20240247407A1

公开(公告)日：2024-07-25

申请号：US18586297

申请日：2024-02-23

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Max Batres ,  Michel Khoury

IPC: C30B29/40 ,  C30B25/02 ,  C30B33/08 ,  H01L21/02 ,  H01L33/00

CPC classification number: C30B29/406 ,  C30B33/08 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L33/0075 ,  C30B25/02

Abstract: Exemplary methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The exemplary methods may further include forming at least one gallium nitride (GaN)-containing region on the nucleation layer, and forming an indium-gallium-nitride (InGaN)-containing layer on the GaN-containing region. A porosified region may be formed on a portion of at least one of the GaN-containing region and the InGaN-containing layer, and an active region may be formed on the porosified region. In embodiments, the porosified region may be characterized by a void fraction of greater than or about 20 vol. %. In further embodiments, the active region may include a greater mole percentage (mol. %) indium than the porosified region or the GaN-containing region. In still further embodiments, the active region may characterized by a peak light emission at a wavelength of greater than or about 620 nm.

公开(公告)号：US11837683B2

公开(公告)日：2023-12-05

申请号：US17197493

申请日：2021-03-10

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Michel Khoury ,  Max Batres

IPC: H01L33/32 ,  H01L33/16 ,  H01L33/08 ,  H01L33/10 ,  H01L33/18 ,  H01L33/00

CPC classification number: H01L33/32 ,  H01L33/007 ,  H01L33/0093 ,  H01L33/08 ,  H01L33/10 ,  H01L33/16 ,  H01L33/18

Abstract: Exemplary processing methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The methods may further include forming first, second, and third, gallium-and-nitrogen-containing regions on the nucleation layer. The first gallium-and-nitrogen-containing region may be porosified, without porosifying the second and third gallium-and-nitrogen containing regions. The methods may still further include forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region. The methods may yet also include forming a third active region on the unporosified third gallium-and-nitrogen-containing region.

公开(公告)号：US20220285584A1

公开(公告)日：2022-09-08

申请号：US17195271

申请日：2021-03-08

Applicant: Applied Materials, Inc.

Inventor： Michel Khoury ,  Lan Yu ,  Michael Chudzik ,  Max Batres

IPC: H01L33/32 ,  H01L33/00 ,  H01L33/46 ,  H01L33/58

Abstract: Exemplary processing methods of forming a semiconductor structure may include forming subpixels on a substrate. Each of the subpixels may include a gallium-and-nitrogen-containing layer formed on an exposed portion of a nucleation layer on the substrate. The subpixels may further include a porosified region formed on or in the gallium-and-nitrogen-containing region, and an active region formed on the porosified region. The active region may include an indium-gallium-and-nitrogen-containing material. The processing methods may further include forming a first reflection layer around one of the subpixels, wherein the first reflection layer includes a first metal layer. The methods may additionally include forming a second reflection layer around another of the subpixels, wherein the second reflection layer includes a second metal that is different than the first metal.

公开(公告)号：US20220259766A1

公开(公告)日：2022-08-18

申请号：US17176367

申请日：2021-02-16

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Max Batres ,  Michel Khoury

IPC: C30B29/40 ,  H01L21/02 ,  C30B33/08 ,  H01L33/00

Abstract: Exemplary methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The exemplary methods may further include forming at least one gallium nitride (GaN)-containing region on the nucleation layer, and forming an indium-gallium-nitride (InGaN)-containing layer on the GaN-containing region. A porosified region may be formed on a portion of at least one of the GaN-containing region and the InGaN-containing layer, and an active region may be formed on the porosified region. In embodiments, the porosified region may be characterized by a void fraction of greater than or about 20 vol. %. In further embodiments, the active region may include a greater mole percentage (mol. %) indium than the porosified region or the GaN-containing region. In still further embodiments, the active region may characterized by a peak light emission at a wavelength of greater than or about 620 nm.

公开(公告)号：US20220165610A1

公开(公告)日：2022-05-26

申请号：US16953567

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Tyler Sherwood ,  Michael Chudzik ,  Siddarth Krishnan

IPC: H01L21/768 ,  H01L21/762 ,  H01L29/06

Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

公开(公告)号：US09748354B2

公开(公告)日：2017-08-29

申请号：US15043883

申请日：2016-02-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei V. Tang ,  Paul F. Ma ,  Steven C. H. Hung ,  Michael Chudzik ,  Siddarth Krishnan ,  Wenyu Zhang ,  Seshadri Ganguli ,  Naomi Yoshida ,  Lin Dong ,  Yixiong Yang ,  Liqi Wu ,  Shih Chung Chen

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/66446 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78681

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.