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    Dummy Bitline Circuitry
    13.
    发明申请
    Dummy Bitline Circuitry 审中-公开

    公开(公告)号：US20190198064A1

    公开(公告)日：2019-06-27

    申请号：US15851341

    申请日：2017-12-21

    Applicant: Arm Limited

    Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

    IPC: G11C7/08 ,  G11C7/22 ,  G11C7/12

    Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

    Dummy Wordline Tracking Circuitry
    14.
    发明申请
    Dummy Wordline Tracking Circuitry 审中-公开

    公开(公告)号：US20190122724A1

    公开(公告)日：2019-04-25

    申请号：US15789715

    申请日：2017-10-20

    Applicant: ARM Limited

    Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

    IPC: G11C11/418 ,  G11C11/412 ,  H01L27/11 ,  H01L23/528

    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

    Integrated circuit using shaping and timing circuitries
    17.
    发明授权
    Integrated circuit using shaping and timing circuitries 有权

    公开(公告)号：US10074410B2

    公开(公告)日：2018-09-11

    申请号：US15282532

    申请日：2016-09-30

    Applicant: ARM Limited

    Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

    IPC: G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08

    CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

    Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

    Integrated Circuit Using Shaping and Timing Circuitries
    19.
    发明申请
    Integrated Circuit Using Shaping and Timing Circuitries 审中-公开

    公开(公告)号：US20180096715A1

    公开(公告)日：2018-04-05

    申请号：US15282532

    申请日：2016-09-30

    Applicant: ARM Limited

    Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

    IPC: G11C7/12 ,  G11C5/14 ,  G11C7/22

    CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

    Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

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