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    INTEGRATED CIRCUIT DEVICE, SYSTEM AND METHOD
    11.
    发明申请
    INTEGRATED CIRCUIT DEVICE, SYSTEM AND METHOD 有权

    公开(公告)号：US20230048259A1

    公开(公告)日：2023-02-16

    申请号：US17817686

    申请日：2022-08-05

    Applicant: Arm Limited

    Inventor： James Edward MYERS ,  Shidhartha DAS

    IPC: G06F12/14 ,  G06F21/72

    Abstract: An integrated circuit device including processing circuitry, communications circuitry configured to provide a communication link with a communication apparatus external to the integrated circuit device, and a memory accessible by the processing circuitry and by the communications circuitry, the memory comprising a memory region to which the processing circuitry has write access and to which the communications circuitry has read access, in which the processing circuitry is configured to write information to the memory region indicative of one or more use conditions of the integrated circuit device, and in which the communications circuitry is configured to access the memory region and to provide the information indicative of the one or more use conditions of the integrated circuit device via the communication link.

    AN APPARATUS AND METHOD FOR PROCESSING A RECEIVED INPUT SIGNAL CONTAINING A SEQUENCE OF DATA BLOCKS
    12.
    发明申请
    AN APPARATUS AND METHOD FOR PROCESSING A RECEIVED INPUT SIGNAL CONTAINING A SEQUENCE OF DATA BLOCKS 审中-公开

    公开(公告)号：US20180278445A1

    公开(公告)日：2018-09-27

    申请号：US15761212

    申请日：2016-09-12

    Applicant: ARM LIMITED

    Inventor： Paul Nicholas WHATMOUGH ,  Shidhartha DAS

    IPC: H04L25/06

    Abstract: An apparatus and method are provided for processing a received input signal comprising a sequence of data blocks. Counter circuitry within the apparatus is arranged to receive a digital representation of the input signal, and for each data block generates a count value indicative of occurrences of a property of the digital representation (for example a rising edge or a falling edge) during an associated data block transmission period. Quantization circuitry then maps each count value to a soft decision value from amongst a predetermined set of soft decision values, where the number of soft decision values in the predetermined set exceeds a number of possible data values of the data block. The output circuitry then generates a digital output signal in dependence on the soft decision values. Such an apparatus has been found to provide a low power technique for a receiver, whilst still enabling the improved sensitivity benefits of using soft decisions to be achieved, and allows the apparatus to be constructed using all digital components.

    CACHE APPARATUS AND A METHOD OF CACHING DATA
    13.
    发明申请
    CACHE APPARATUS AND A METHOD OF CACHING DATA 审中-公开

    公开(公告)号：US20180203802A1

    公开(公告)日：2018-07-19

    申请号：US15864062

    申请日：2018-01-08

    Applicant: ARM Limited

    Inventor： Ricardo Daniel Queiros ALVES ,  Nikos NIKOLERIS ,  Shidhartha DAS ,  Andreas Lars SANDBERG

    IPC: G06F12/0864 ,  G06F12/0888 ,  G06F12/0862

    CPC classification number: G06F12/0864 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/507 ,  G06F2212/602 ,  Y02D10/13

    Abstract: A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. A set associative tag storage structure stores a tag value for each cache block, with that set associative tag storage structure being shared by the first and second data arrays. Control circuitry applies an access likelihood policy to determine, for each set, a subset of the cache blocks of that set to be stored within the first data array. Access circuitry is then responsive to an access request to perform a lookup operation within an identified set of the set associative tag storage structure overlapped with an access operation to access within the first data array the subset of the cache blocks for the identified set. In the event of a hit condition being detected that identifies a cache block present in the first data array, that access request is then processed using the cache block accessed within the first data array. If instead a hit condition is detected that identifies a cache block absent in the first data array, then a further access operation is performed to access the identified cache block within a selected way of the second data array. Such a cache structure provides a high performance and energy efficient mechanism for storing cached data.

    Apparatus and Method for Detecting a Resonant Frequency Giving Rise to an Impedance Peak in a Power Delivery Network
    15.
    发明申请
    Apparatus and Method for Detecting a Resonant Frequency Giving Rise to an Impedance Peak in a Power Delivery Network 有权
    用于检测在馈电网络中提高到阻抗峰值的谐振频率的装置和方法

    公开(公告)号：US20170030954A1

    公开(公告)日：2017-02-02

    申请号：US15172101

    申请日：2016-06-02

    Applicant: ARM Limited

    Inventor： Paul Nicholas WHATMOUGH ,  Shidhartha DAS ,  David Michael BULL

    IPC: G01R27/26

    CPC classification number: G01R23/07 ,  G01R23/02 ,  G01R23/04 ,  G01R27/04 ,  G01R27/26 ,  G01R27/32

    Abstract: An apparatus and method are provided for detecting a resonant frequency giving rise to an impedance peak in a power delivery network used to provide a supply voltage. The apparatus includes resonant frequency detection circuitry that comprises test frequency control circuitry and a loading circuit. The test frequency control circuitry is arranged to generate control signals to indicate a sequence of test frequencies. A loading circuit is controlled by the control signals and operates from the supply voltage. In particular, in response to each test frequency indicated by the control signals, the loading circuit draws a duty-cycled current load through the power delivery network at that test frequency. Operation of the loading circuit produces a measurable property whose value varies in dependence on the supply voltage, thus enabling the resonant frequency to be determined from a variation in the value of that measurable property.

    Abstract translation: 提供了一种用于检测在用于提供电源电压的功率传递网络中产生阻抗峰值的谐振频率的装置和方法。 该装置包括谐振频率检测电路，其包括测试频率控制电路和加载电路。 测试频率控制电路被布置成产生控制信号以指示测试频率的序列。 加载电路由控制信号控制，并从供电电压进行工作。 特别地，响应于由控制信号指示的每个测试频率，负载电路在该测试频率下通过电力输送网络抽取占空比的电流负载。 加载电路的操作产生可测量的性质，其值根据电源电压而变化，从而可以根据该可测量特性的值的变化来确定谐振频率。

    METHODS AND APPARATUS FOR WORKLOAD SCHEDULING
    17.
    发明公开
    METHODS AND APPARATUS FOR WORKLOAD SCHEDULING 审中-公开

    公开(公告)号：US20240036923A1

    公开(公告)日：2024-02-01

    申请号：US17874658

    申请日：2022-07-27

    Applicant: Arm Limited

    Inventor： Rishav ROY ,  Supreet JELOKA ,  Shidhartha DAS ,  Rahul MATHUR

    IPC: G06F9/48

    CPC classification number: G06F9/4893

    Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of processing elements having a spatial layout, and control circuitry to assign workloads to said plurality of processing elements. The control circuitry is configured to, based on a timing parameter, determine one or more active processing elements to deactivate; determine, based on the spatial layout, one or more inactive processing elements to activate; and deactivate said one or more active processing elements and activate said one or more inactive processing elements.

    MEMORY SCANNING OPERATION IN RESPONSE TO COMMON MODE FAULT SIGNAL
    18.
    发明申请
    MEMORY SCANNING OPERATION IN RESPONSE TO COMMON MODE FAULT SIGNAL 有权

    公开(公告)号：US20210279124A1

    公开(公告)日：2021-09-09

    申请号：US17261217

    申请日：2019-06-06

    Applicant: Arm Limited

    Inventor： Milosch MERIAC ,  Emre ÖZER ,  Xabier ITURBE ,  Balaji VENU ,  Shidhartha DAS

    IPC: G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/30

    Abstract: An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

    METHODS AND APPARATUS FOR ANOMALY RESPONSE
    19.
    发明申请
    METHODS AND APPARATUS FOR ANOMALY RESPONSE 审中-公开

    公开(公告)号：US20190391888A1

    公开(公告)日：2019-12-26

    申请号：US16014154

    申请日：2018-06-21

    Applicant: Arm Limited

    Inventor： Milosch MERIAC ,  Xabier ITURBE ,  Emre OZER ,  Balaji VENU ,  Shidhartha DAS

    IPC: G06F11/20 ,  G06F11/14 ,  G06F11/16

    Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

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