利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

50 条记录 (耗时 0.184 秒)

    METHOD FOR FORMING CARBON SILICON ALLOY (CSA) AND STRUCTURES THEREOF
    11.
    发明申请
    METHOD FOR FORMING CARBON SILICON ALLOY (CSA) AND STRUCTURES THEREOF 审中-公开
    形成碳硅合金（CSA）的方法及其结构

    公开(公告)号：US20090267118A1

    公开(公告)日：2009-10-29

    申请号：US12111377

    申请日：2008-04-29

    申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Rainer Loesing ,  Dominic J. Schepis

    发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Rainer Loesing ,  Dominic J. Schepis

    IPC分类号： H01L49/00 ,  H01L21/20

    CPC分类号： H01L21/02529 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Methods for forming carbon silicon alloy (CSA) and structures thereof are disclosed. The method provides improvement in substitutionality and deposition rate of carbon in epitaxially grown carbon silicon alloy layers (i.e., substituted carbon in Si lattice). In one embodiment of the disclosed method, a carbon silicon alloy layer is epitaxially grown on a substrate at an intermediate temperature with a silicon precursor, a carbon (C) precursor in the presence of an etchant and a trace amount of germanium material (e.g., germane (GeH4)). The intermediate temperature increases the percentage of substitutional carbon in epitaxially grown CSA layer and avoids any tendency for silicon carbide to form. The presence of the trace amount of germanium material, of approximately less than 1% to approximately 5%, in the resulting epitaxial layer, has an effect of stabilizing and enhancing deposition/growth rate without compromising the tensile stress of CSA layer formed thereby.

    摘要翻译： 公开了形成碳硅合金（CSA）的方法及其结构。 该方法提供了外延生长碳硅合金层（即Si晶格中的取代碳）的碳的取代度和沉积速率的改善。 在所公开的方法的一个实施方案中，在中间温度下在硅衬底，碳（C）前体，在蚀刻剂和痕量锗材料存在下，在衬底上外延生长碳硅合金层（例如， （GeH4））。 中间温度增加外延生长的CSA层中的替代碳的百分比，并避免形成碳化硅的任何倾向。 在所得外延层中痕量锗材料的存在大约小于1％至约5％具有稳定和增强沉积/生长速率的效果，而不会影响由此形成的CSA层的拉伸应力。

    CMOS device structure with improved PFET gate electrode
    14.
    发明授权
    CMOS device structure with improved PFET gate electrode 有权
    具有改进的PFET栅电极的CMOS器件结构

    公开(公告)号：US06838695B2

    公开(公告)日：2005-01-04

    申请号：US10304163

    申请日：2002-11-25

    申请人： Bruce B. Doris ,  Ashima B. Chakravarti ,  Kevin K. Chan ,  Daniel A. Uriarte

    发明人： Bruce B. Doris ,  Ashima B. Chakravarti ,  Kevin K. Chan ,  Daniel A. Uriarte

    IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/04

    CPC分类号： H01L29/4925 ,  H01L21/28044 ,  H01L21/823842

    摘要： A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.

    摘要翻译： 半导体器件结构包括衬底，设置在衬底上的电介质层，设置在电介质层上的第一和第二堆叠。 第一堆叠包括设置在电介质层上的第一硅层，设置在第一硅层上的硅锗层，设置在硅锗层上的第二硅层和设置在第二硅层上的第三硅层。 第二堆叠包括布置在电介质层上的第一硅层和设置在第一硅层上的第二硅层。 或者，硅锗层包括硼。

    Method for reducing the microloading effect in a chemical vapor deposition reactor
    15.
    发明授权
    Method for reducing the microloading effect in a chemical vapor deposition reactor 失效

    公开(公告)号：US06555166B2

    公开(公告)日：2003-04-29

    申请号：US09895378

    申请日：2001-06-29

    申请人： Oleg Gluschenkov ,  Ashima B. Chakravarti

    发明人： Oleg Gluschenkov ,  Ashima B. Chakravarti

    IPC分类号： C23C1600

    CPC分类号： C23C16/45502 ,  C23C16/455

    摘要： A method is provided for reducing the microloading effect in a CVD process for depositing a film on a substrate. This method is particularly useful in a single-wafer CVD reactor. The microloading effect is reduced by identifying a growth-rate-limiting reactant; calculating a dilution factor (the ratio of the gas flow rate of the growth-rate-limiting reactant to the total gas flow rate in the reactor); and adjusting the film growth rate and/or the dilution factor to satisfy a numerical criterion for reducing the microloading effect. The criterion is satisfied when the film growth rate is reduced, or the dilution factor is increased, so that the dilution factor is equal to or greater than a quantity which includes the film growth rate as a factor. The film growth rate and dilution factor may be adjusted independently. The gap between the showerhead and the substrate in the CVD reactor may be adjusted to satisfy the numerical criterion. The gap may advantageously be reduced to less than 5 mm, preferably to about 100 &mgr;m. A gap in the range 50 &mgr;m-5 mm reduces a characteristic distance which is a factor in the above-mentioned quantity, so that the criterion becomes easier to meet.

    High throughput chemical vapor deposition process capable of filling high aspect ratio structures
    16.
    发明授权
    High throughput chemical vapor deposition process capable of filling high aspect ratio structures 失效
    能够填充高纵横比结构的高通量化学气相沉积工艺

    公开(公告)号：US6030881A

    公开(公告)日：2000-02-29

    申请号：US72759

    申请日：1998-05-05

    申请人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    发明人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    IPC分类号： C23C16/04 ,  C23C16/40 ,  C23C16/56 ,  H01L21/762

    CPC分类号： H01L21/76224 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56

    摘要： A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.

    摘要翻译： 提供了一种通过使用具有不同蚀刻速率 - 沉积速率（蚀刻/去除）比率的沉积和蚀刻步骤顺序的高密度等离子体（HDP）沉积工艺来填充高纵横比间隙而无空隙形成的方法。 第一步使用小于1的蚀刻/剥离比快速填充间隙。 第一步在打开间隙之前中断。 第二步使用大于1的蚀刻/剥离比来扩大间隙。 在形成间隙的元件的角部暴露之前停止第二步骤。 可以重复这些步骤，直到间隙的纵横比减小，使得无空隙间隙填充成为可能。 可以优化每个步骤的蚀刻/剥离比和持续时间，以实现高通量和高纵横比填充间隙。

    SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE
    19.
    发明申请
    SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE 有权
    硅锗膜形成方法和结构

    公开(公告)号：US20120205749A1

    公开(公告)日：2012-08-16

    申请号：US13025474

    申请日：2011-02-11

    申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

    发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

    IPC分类号： H01L27/092 ,  H01L21/762 ,  H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/76224 ,  H01L21/823807

    摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

    摘要翻译： 在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。 使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。 可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。 导致沉积的SiGe基本上没有生长边缘效应。