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公开(公告)号：US20220126294A1
公开(公告)日：2022-04-28
申请号：US17432580
申请日：2021-01-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiaochen MA , Ce NING , Guangcai YUAN , Xin GU , Zhengliang LI
Abstract: A biochip and a method for manufacturing the same are provided. The biochip includes: a guide layer; a channel layer on the guide layer, wherein the channel layer has therein a plurality of first channels extending in a first direction; a plurality of second channels extending in a second direction, wherein each of the plurality of second channels is in communication with the plurality of first channels, the plurality of second channels are in a layer where the channel layer is located, or in a layer where the channel layer and the guide layer are located; an encapsulation cover plate on a side of the channel layer distal to the guide layer; and a driving unit configured to drive biomolecules to move.
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公开(公告)号：US20210229088A1
公开(公告)日：2021-07-29
申请号：US16643464
申请日：2019-03-11
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiaochen MA , Guangcai YUAN , Ce NING , Zhengliang LI
Abstract: A microfluidic channel and a preparation method and an operation method thereof. The microfluidic channel includes: a channel structure, including a channel for a liquid sample to flow through and a channel wall surrounding the channel. The channel wall includes an electrolyte layer made of an electrolyte material; and a control electrode layer, at a side of the electrolyte layer away from the channel. The control electrode layer overlaps with the electrolyte layer with respect to the channel.
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公开(公告)号：US20210134900A1
公开(公告)日：2021-05-06
申请号：US16639298
申请日：2019-03-29
Inventor： Mingxiao JIANG , Weifeng ZHOU , Ce NING
Abstract: A light emitting substrate and a manufacturing method thereof, and an electronic device are provided, the method includes: forming a pixel definition layer by a patterning process using a first mask, in which the pixel definition layer includes an opening and a partition portion defining the opening; forming a first electrode, in which the first electrode includes a first portion covering at least a part of the partition portion and includes a second portion in the opening; and forming an auxiliary electrode by a patterning process using the first mask, in which the auxiliary electrode is electrically connected with the first electrode, and the auxiliary electrode is on the partition portion.
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14.发明申请公开(公告)号：US20160035760A1
公开(公告)日：2016-02-04
申请号：US14422342
申请日：2014-06-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: H01L27/12
CPC classification number: H01L27/1248 , G02F2001/134372 , H01L27/1259 , H01L27/1288
Abstract: The invention belongs to the field of display technology, and particularly provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and a thin film transistor and driving electrodes provided on the base substrate, the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, the driving electrodes include a slit-shaped electrode and a plate-shaped electrode which are located in different layers and at least partially overlap with each other in the orthographic projection direction, the source, the drain and the active layer are formed so that part of their bottom surfaces are located in the same plane, and a resin layer is further provided between the thin film transistor and the plate-shaped electrode.
Abstract translation: 本发明属于显示技术领域，特别是提供阵列基板及其制造方法以及显示装置。 阵列基板包括基底基板和设置在基底基板上的薄膜晶体管和驱动电极，薄膜晶体管包括栅极，栅极绝缘层，有源层，源极和漏极，驱动电极包括 狭缝状电极和板状电极，其位于不同的层中并且在正投影方向上彼此至少部分重叠，源极，漏极和有源层形成为使得它们的底表面的一部分位于 在同一平面内，在薄膜晶体管和板状电极之间进一步设置树脂层。
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15.发明申请公开(公告)号：US20250098212A1
公开(公告)日：2025-03-20
申请号：US18963664
申请日：2024-11-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jie HUANG , Jiayu HE , Ce NING , Zhengliang LI , Hehe HU , Fengjuan LIU , Nianqi YAO , Kun ZHAO , Tianmin ZHOU , Jiushi WANG , Zhongpeng TIAN
IPC: H01L29/786 , G02F1/1368 , H01L27/12 , H01L29/66
Abstract: The present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method for manufacturing the same, an array substrate and a display device. An active layer of the thin film transistor includes at least two metal oxide semi-conductor layers, the at least two metal oxide semi-conductor layers include a channel layer and a first protection layer, and metals in the channel layer include at least one of indium, gallium and zinc. Praseodymium is doped into the channel layer. And, in the channel layer, a number density of praseodymium atoms in the channel layer gradually decreases with a distance from the first protection layer.
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Patent Agency Ranking
公开(公告)号：US20240371887A1
公开(公告)日：2024-11-07
申请号：US18773582
申请日：2024-07-16
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yuhang LU , Fengjuan LIU , Hehe HU , Zhengliang LI , Ce NING , Guangcai YUAN , Dandan ZHOU , Cheng XU
IPC: H01L27/12 , G02F1/1333 , G02F1/1362 , G02F1/1368 , H01L25/075 , H01L29/66 , H01L29/786 , H10K59/121
Abstract: A thin film transistor includes a first active layer, a second active layer, a first electrode, a second electrode and a third electrode. The first active layer includes a first surface away from a substrate. The second active layer includes a second surface in contact with the first surface. The first electrode, the first active layer and the second active layer have an overlapping region. The second electrode, the first active layer and the second active layer have an overlapping region. The third electrode, the first active layer and the second active layer have an overlapping region, and the third electrode is opposite to the second electrode. The second surface is located within the first surface, and a distance between at least part of a border of the second surface and a border of the first surface is less than or equal to 0.5 μm.
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17.发明公开公开(公告)号：US20240355978A1
公开(公告)日：2024-10-24
申请号：US18254210
申请日：2022-04-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Nianqi YAO , Zhongpeng TIAN , Ce NING , Zhengliang LI , Hehe HU , Jie HUANG , Jiayu HE , Feifei LI , Kun ZHAO , Yimin CHEN
IPC: H01L33/62 , G02F1/13357 , H05K3/46
CPC classification number: H01L33/62 , G02F1/133603 , H05K3/4688
Abstract: A circuit board includes a substrate and a stress neutral layer disposed on a side of the substrate. The stress neutral layer includes one or more first metal layers and one or more second metal layers. The one or more second metal layers and the one or more first metal layers are stacked. At least one of the one or more first metal layers is made of a material for generating a tensile stress, and at least one of the one or more second metal layers is made of a material for generating a compressive stress.
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公开(公告)号：US20240329478A1
公开(公告)日：2024-10-03
申请号：US18638710
申请日：2024-04-18
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangcai YUAN , Hehe HU , Ce NING , Hui GUO , Fengjuan LIU , Dongfang WANG , Zhengliang LI , Jiayu HE
IPC: G02F1/1368 , G02F1/1362 , H01L27/12
CPC classification number: G02F1/1368 , G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F1/136295 , H01L27/124 , H01L27/1255 , H01L27/1259
Abstract: An array substrate and a manufacturing method therefor, and a display apparatus are provided. The array substrate includes an underlay substrate, and at least one first transistor, at least one data line and at least one pixel electrode disposed on the underlay substrate. The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the underlay substrate, and orthographic projections of the first gate and the first active layer on the underlay substrate are at least partially overlapped. The first active layer is electrically connected to the data line and the pixel electrode, respectively. The data line is located on a side of the first active layer close to the underlay substrate, and the pixel electrode is located on a side of the first gate away from the underlay substrate.
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公开(公告)号：US20240329472A1
公开(公告)日：2024-10-03
申请号：US18646815
申请日：2024-04-26
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xinhong LU , Yan QU , Ce NING , Wei YANG , Zhanfeng CAO , Jingshang ZHOU , Lizhong WANG
IPC: G02F1/1362 , G02F1/1368
CPC classification number: G02F1/136222 , G02F1/136209 , G02F1/136286 , G02F1/1368
Abstract: A color filter, a preparation method therefore, an array substrate and a display device are provided. The color filter includes a plurality of filter units (20) provided on a base substrate (10) for transmitting light of different colors, and a light shielding layer (30) located between adjacent filter units (20) for transmitting light of different colors. The filter unit (20) includes a first surface facing the base substrate (10), a second surface facing away from the base substrate, and a third surface connecting the first surface and the second surface. The light shielding layer (30) is provided on the third surface of at least one of two adjacent filter units (20) transmitting light of different colors.
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公开(公告)号：US20240255820A1
公开(公告)日：2024-08-01
申请号：US18017413
申请日：2022-03-31
Applicant: BOE Technology Group Co., Ltd.
Inventor： Yunping DI , Lizhong WANG , Ce NING , Binbin TONG , Liping LEI , Jianbo XIAN
IPC: G02F1/1368 , G02F1/1362 , H01L27/12
CPC classification number: G02F1/1368 , G02F1/136209 , G02F1/136227 , G02F1/136295 , H01L27/1244 , H01L27/1288
Abstract: Provided is a substrate. The substrate includes a base substrate; and a plurality of sub-pixel structures arranged in an array on the base substrate, wherein the sub-pixel structure comprises: a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain; an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer; a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and a filling block disposed at the first via hole.
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