公开(公告)号：US20140153680A1

公开(公告)日：2014-06-05

申请号：US13691482

申请日：2012-11-30

Applicant: BROADCOM CORPORATION

Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

IPC: H04L7/033

CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

公开(公告)号：US20130229232A1

公开(公告)日：2013-09-05

申请号：US13867883

申请日：2013-04-22

Applicant: BROADCOM CORPORATION

Inventor： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC: H03F3/16

CPC classification number: H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03F2203/45706

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

Abstract translation: 为高速收发器提供了高带宽电路。 该电路可以包括组合电容器分离，电感树结构和各种带宽扩展技术的放大器，例如并联峰值，串联峰值和T形线圈峰值，以支持45Gbs / s及以上的数据速率，同时减少数据抖动。 电感树结构的电感元件还可以包括高阻抗传输线，从而简化了实现。 此外，电感器和t-线圈的容易识别的金属结构，负载电容器的相等分配以及对称的电感树结构可以简化收发器实现，但不限于时钟数据恢复电路。

公开(公告)号：US09184737B1

公开(公告)日：2015-11-10

申请号：US14332106

申请日：2014-07-15

Applicant: Broadcom Corporation

Inventor： Tamer Ali ,  Jun Cao

IPC: H03M1/10 ,  H03K5/135 ,  H03M1/12

CPC classification number: H04B17/21 ,  H03K5/135 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/1245 ,  H04L7/0012

Abstract: A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

Abstract translation: 一种设备包括进程减轻时序（PMT）电路。 PMT电路允许调整时钟信号，同时补偿PMT电路内的过程变化。 PMT电路可以包括过程减缓缓冲器（PMB）电路。 PMB电路可以利用复制电路和经校准的电阻来产生校准偏置电压。 校准的偏置电压可用于驱动元件缓冲器电路以产生校准的电流响应。 校准的电流响应可以对应于组件缓冲器电路的选择的输出阻抗。 选择输出阻抗可以与可变电容一起使用，以独立于PMT电路内的过程变化的方式调整时钟信号。

公开(公告)号：US20160182080A1

公开(公告)日：2016-06-23

申请号：US14616566

申请日：2015-02-06

Applicant: BROADCOM CORPORATION

Inventor： Anand Jitendra Vasani ,  Ali Nazemi ,  Jun Cao ,  Afshin Momtaz

IPC: H03M1/68 ,  H03M1/10 ,  H03M1/74 ,  H03M1/00

CPC classification number: H03M1/68 ,  H03M1/002 ,  H03M1/068 ,  H03M1/1028 ,  H03M1/1047 ,  H03M1/74 ,  H03M1/80

Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

Abstract translation: 低功率可重构电压模式数模转换器（DAC）驱动电路包括第一和第二电源电压以及多个DAC单元。 每个DAC单元耦合到数字输入的相应位。 DAC单元配置为保持恒定的输出阻抗。 每个DAC单元包括一个或多个互补开关对，其基于数字输入的相应位将一个或多个相应阻抗的第一节点耦合到第一或第二电源电压中的一个。 一个或多个相应阻抗的第二节点耦合到输出节点。

公开(公告)号：US20160164156A1

公开(公告)日：2016-06-09

申请号：US14638455

申请日：2015-03-04

Applicant: Broadcom Corporation

Inventor： Guansheng Li ,  Jun Cao

IPC: H01P1/26

CPC classification number: H03H11/0405 ,  H03H11/53 ,  H04L25/0298

Abstract: A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

Abstract translation: 非线性阻抗终止传输线。 非线性阻抗可以用背对背连接的逆变器对实现。 该对用作非线性电阻。 也可以提供过程，电压，温度（PVT）跟踪电路来改善PVT跟踪，晶体管的电阻锁定到校准电阻器上。 复制电路不会出现在信号路径中，不会增加电容性负载。

公开(公告)号：US09344268B1

公开(公告)日：2016-05-17

申请号：US14668165

申请日：2015-03-25

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Burak Catli ,  Wayne Wah-Yuen Wong ,  Kangmin Hu ,  Hyo Gyuem Rhew ,  Delong Cui ,  Jun Cao ,  Bo Zhang ,  Afshin Doctor Momtaz

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04J3/0685 ,  H04J3/047 ,  H04L7/0025

Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Abstract translation: 相位对准架构增强了通信系统的性能。 即使在非常高的速度下，分频时钟的分频时钟（例如，差分同相（I）和正交（Q））与主时钟对准，其中分频时钟的偏移变化与主时钟周期相当。 相位对准的改进有助于超高速通信。

公开(公告)号：US09136797B2

公开(公告)日：2015-09-15

申请号：US14042274

申请日：2013-09-30

Applicant: Broadcom Corporation

Inventor： Kuo-J Huang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz ,  Iuri Mehr ,  Ramon Alejandro Gomez

IPC: H03F3/45 ,  H03F1/32

CPC classification number: H03F1/3205 ,  H03F1/3211 ,  H03F1/3241 ,  Y10T29/49016

Abstract: Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

Abstract translation: 这里描述了利用负增益自适应地抑制放大器中的谐波失真的技术。 放大器包括并联耦合的第一放大级和第二放大级。 第一个放大器级具有正增益。 第二放大器级具有负增益以抑制包括放大器的系统的总谐波失真。 放大器还包括耦合到第一放大器级和第二放大器级的并联峰值电路，以增加放大器能够操作的最大工作频率。

公开(公告)号：US09065464B2

公开(公告)日：2015-06-23

申请号：US14040467

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/1215

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

Abstract translation: 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。

公开(公告)号：US20140126613A1

公开(公告)日：2014-05-08

申请号：US13671340

申请日：2012-11-07

Applicant: BROADCOM CORPORATION

Inventor： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC: H03D3/02

CPC classification number: H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US20140055180A1

公开(公告)日：2014-02-27

申请号：US13622223

申请日：2012-09-18

Applicant: BROADCOM CORPORATION

Inventor： Adesh Garg ,  Jun Cao

IPC: H03K3/02 ,  H03L7/06

CPC classification number: H03K5/135 ,  G06F1/10

Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.

Abstract translation: 时钟驱动器包括运行到集成电路芯片的多个通道的时钟互连，该互连包括正时钟线和负时钟线。 时钟发生器产生时钟信号和源电感器，时钟发生器通过该电感器吸取直流电源，有助于将时钟信号驱动到互连。 源电感可以是可调谐的。 分布式（或可调谐）电感器连接到源电感器和互连端之间的正和负时钟线并且位于其间。 多个分布式电感器可以被定位并且可选地调谐，以便在时钟信号中产生具有基本相似的质量和幅度的谐振响应，并且输送到多个通道。 任何分布式和源极感应器都可以切换以改变分布式电感器的电感，从而改变不同通信标准的通道中的时钟频率。