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    Electrical erasable programmable memory transconductance testing
    11.
    发明授权
    Electrical erasable programmable memory transconductance testing 有权
    电可擦除可编程存储器跨导测试

    公开(公告)号：US07545679B1

    公开(公告)日：2009-06-09

    申请号：US11966068

    申请日：2007-12-28

    申请人： Richard K. Eguchi ,  Chen He ,  Ronald J. Syzdek

    发明人： Richard K. Eguchi ,  Chen He ,  Ronald J. Syzdek

    IPC分类号： G11C16/00

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5002 ,  G11C2029/5006

    摘要： A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit cells of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics by reading each bit cell to determine whether its transconductance is less than desirable.

    摘要翻译： 测试方法确定闪存EEPROM电路的阵列是否具有缺陷的跨导（gm）的位单元。 该方法将阵列的所有比特单元预先调整到特定的编程状态，然后通过读取每个比特单元来确定其中的任何一个比特单元是否表现出不期望的运行特性，以确定其跨导是否小于期望值。

    Adaptive write procedures for non-volatile memory
    12.
    发明授权
    Adaptive write procedures for non-volatile memory 有权
    非易失性存储器的自适应写入程序

    公开(公告)号：US08509001B2

    公开(公告)日：2013-08-13

    申请号：US13170009

    申请日：2011-06-27

    申请人： Chen He ,  Richard K. Eguchi

    发明人： Chen He ,  Richard K. Eguchi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/30

    摘要： A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A level of the voltage is compared to a reference. If the level of the voltage is below the reference, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells, wherein the reduced number of memory cells is a first subset of the memory cells.

    摘要翻译： 一种方法包括使用电荷泵的电压对存储器阵列的存储器单元执行写入操作到第一逻辑状态。 使用电荷泵的电压对存储器阵列的存储单元执行写入操作的一部分。 将电压的电平与参考值进行比较。 如果电压的电平低于参考值，则通过在减少数量的存储器单元上提供电压来减小电荷泵上的负载，继续以电压水平升高的写入操作，其中减少数量的存储器单元是 存储器单元的第一子集。

    Temperature-based adaptive erase or program parallelism
    14.
    发明授权
    Temperature-based adaptive erase or program parallelism 有权
    基于温度的自适应擦除或程序并行

    公开(公告)号：US09224478B2

    公开(公告)日：2015-12-29

    申请号：US13787799

    申请日：2013-03-06

    申请人： Richard K. Eguchi ,  Jon S. Choy ,  Chen He ,  Kelly K. Taylor

    发明人： Richard K. Eguchi ,  Jon S. Choy ,  Chen He ,  Kelly K. Taylor

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C7/04 ,  G11C16/14 ,  G11C16/30 ,  G11C16/34

    CPC分类号： G11C16/10 ,  G11C7/04 ,  G11C16/14 ,  G11C16/30 ,  G11C16/349

    摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.

    摘要翻译： 一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。 使用电荷泵的电压对存储器单元执行一部分操作。 将存储器阵列的温度与阈值进行比较。 如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

    Non-volatile memory (NVM) with adaptive write operations
    15.
    发明授权
    Non-volatile memory (NVM) with adaptive write operations 有权
    具有自适应写入操作的非易失性存储器（NVM）

    公开(公告)号：US09082510B2

    公开(公告)日：2015-07-14

    申请号：US13616169

    申请日：2012-09-14

    申请人： Chen He ,  Richard K. Eguchi

    发明人： Chen He ,  Richard K. Eguchi

    IPC分类号： G11C16/10 ,  G11C11/56

    CPC分类号： G11C11/5628 ,  G11C16/10

    摘要： A method of performing a write operation on memory cells of a memory array includes applying a first plurality of pulses the write operation on the memory cells in accordance with a first predetermined ramp rate, wherein the first plurality of pulses is a predetermined number of pulses; performing a comparison of a threshold voltage of a subset of the memory cells with an interim verify voltage; and if a threshold voltage of any of the subset of memory cells fails the comparison with the interim verify voltage, continuing the write operation by applying a second plurality of pulses on the memory cells in accordance with a second predetermined ramp rate which has an increased ramp rate as compared to the first predetermined ramp rate.

    摘要翻译： 对存储器阵列的存储单元执行写入操作的方法包括：根据第一预定斜率对存储器单元施加写入操作的第一多个脉冲，其中所述第一多个脉冲是预定数量的脉冲; 执行存储器单元的子集的阈值电压与临时验证电压的比较; 并且如果存储器单元的任何子集的阈值电压失败与临时验证电压的比较，则通过根据具有增加的斜坡的第二预定斜坡速率在存储器单元上施加第二多个脉冲来继续写入操作 速率与第一预定斜坡率相比。

    Adaptive write procedures for non-volatile memory using verify read
    16.
    发明授权
    Adaptive write procedures for non-volatile memory using verify read 有权
    使用验证读取的非易失性存储器的自适应写入程序

    公开(公告)号：US08432752B2

    公开(公告)日：2013-04-30

    申请号：US13169989

    申请日：2011-06-27

    申请人： Richard K. Eguchi ,  Chen He

    发明人： Richard K. Eguchi ,  Chen He

    IPC分类号： G11C7/00

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/349

    摘要： A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A determination is made if the voltage insufficient for performing the write operation on the memory cells of the memory array. If a level of the voltage is insufficient, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells. The reduced number of memory cells is a first subset of the memory cells.

    摘要翻译： 一种方法包括使用电荷泵的电压对存储器阵列的存储器单元执行写入操作到第一逻辑状态。 使用电荷泵的电压对存储器阵列的存储单元执行写入操作的一部分。 如果对存储器阵列的存储单元执行写入操作的电压不足，则确定。 如果电压水平不足，则通过在减少数量的存储单元上提供电压来减小电荷泵上的负载，继续以电压水平升高的写入操作。 存储器单元的数量减少是存储器单元的第一子集。

    Non-volatile memory (NVM) erase operation with brownout recovery technique
    17.
    发明授权
    Non-volatile memory (NVM) erase operation with brownout recovery technique 有权
    具有欠压恢复技术的非易失性存储器（NVM）擦除操作

    公开(公告)号：US08289773B2

    公开(公告)日：2012-10-16

    申请号：US12942260

    申请日：2010-11-09

    申请人： Richard K. Eguchi ,  Jon S. Choy ,  Richard K. Glaeser ,  Chen He ,  Peter J. Kuhn

    发明人： Richard K. Eguchi ,  Jon S. Choy ,  Richard K. Glaeser ,  Chen He ,  Peter J. Kuhn

    IPC分类号： G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/107 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459

    摘要： A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.

    摘要翻译： 擦除非易失性存储器的方法包括：在非易失性存储器上执行第一预擦除程序步骤; 在第一预擦除程序步骤期间确定非易失性存储器未能正确编程; 响应于确定非易失性存储器无法正确编程，对非易失性存储器执行第一软程序步骤; 确定非易失性存储器软编程正确; 响应于确定在第一软程序步骤期间正确地编程非易失性存储器的软件，在非易失性存储器上执行第二预擦除程序步骤; 以及对所述非易失性存储器执行擦除步骤。 该方法可以使用非易失性存储器控制器来执行。

    Stress-based techniques for detecting an imminent read failure in a non-volatile memory array
    18.
    发明授权
    Stress-based techniques for detecting an imminent read failure in a non-volatile memory array 有权
    用于检测非易失性存储器阵列中即将发生的读取故障的基于压力的技术

    公开(公告)号：US08977914B2

    公开(公告)日：2015-03-10

    申请号：US13483968

    申请日：2012-05-30

    申请人： Richard K. Eguchi ,  Chen He

    发明人： Richard K. Eguchi ,  Chen He

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1048 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C29/06 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/0411

    摘要： A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check. In this case, the margin read verify voltage level is different from a normal read verify voltage level.

    摘要翻译： 一种用于检测非易失性存储器阵列中即将发生的读取故障的技术包括将批量读取应力应用于非易失性存储器阵列的多个单元，并确定多个单元是否呈现出不可校正的纠错码（ECC）读取 在大容量读取应力之后的余量读取验证电压电平期间的阵列完整性检查。 当在阵列完整性检查期间多个小区呈现不可校正的ECC读取时，该技术还包括提供多个小区即将发生的读取失败的指示。 在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。

    Temperature-Based Adaptive Erase or Program Parallelism
    19.
    发明申请
    Temperature-Based Adaptive Erase or Program Parallelism 有权
    基于温度的自适应擦除或程序并行性

    公开(公告)号：US20140254285A1

    公开(公告)日：2014-09-11

    申请号：US13787799

    申请日：2013-03-06

    申请人： Richard K. Eguchi ,  Jon S. Choy ,  Chen He ,  Kelly K. Taylor

    发明人： Richard K. Eguchi ,  Jon S. Choy ,  Chen He ,  Kelly K. Taylor

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C7/04 ,  G11C16/14 ,  G11C16/30 ,  G11C16/349

    摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.

    摘要翻译： 一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。 使用电荷泵的电压对存储器单元执行一部分操作。 将存储器阵列的温度与阈值进行比较。 如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

    Non-volatile memory (NVM) with imminent error prediction
    20.
    发明授权
    Non-volatile memory (NVM) with imminent error prediction 有权
    非易失性存储器（NVM）具有迫在眉睫的错误预测

    公开(公告)号：US08782478B2

    公开(公告)日：2014-07-15

    申请号：US14048362

    申请日：2013-10-08

    申请人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilmann, II

    发明人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilmann, II

    IPC分类号： G11C29/00

    CPC分类号： G11C29/38 ,  G06F11/073 ,  G06F11/0754 ,  G11C16/3418

    摘要： A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.

    摘要翻译： 非易失性存储器系统包括存储器阵列和存储器控制器。 存储器控制器被配置为执行阵列的第一阵列完整性读取操作，直到检测到错误。 控制器还被配置为确定错误不是纠错码（ECC）可校正。 与误差相关联的第一字线电压被表征为第一阈值电压。 控制器还被配置为执行阵列的第二阵列完整性读操作。 第二阵列完整性读操作包括使用偏离第一阈值电压的字线读取电压读取阵列，并且基于预定的宽度偏移参考值。 最后，控制器被配置为检查由第二阵列完整性读操作产生的校验和值，以确定何时指示存储器阵列中即将发生的故障。