公开(公告)号：US10340906B2

公开(公告)日：2019-07-02

申请号：US15779432

申请日：2017-01-23

申请人： SOUTHEAST UNIVERSITY ,  SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE

发明人： Weifeng Sun ,  Yunwu Zhang ,  Kuo Yu ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC分类号： H02M3/07 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0185 ,  H01L27/07 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

摘要： Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

公开(公告)号：US11322606B2

公开(公告)日：2022-05-03

申请号：US16969437

申请日：2019-10-21

申请人： SOUTHEAST UNIVERSITY

发明人： Weifeng Sun ,  Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Xinyi Tao ,  Ningbo Li ,  Longxing Shi

IPC分类号： H01L29/778

摘要： A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US09159818B2

公开(公告)日：2015-10-13

申请号：US14349632

申请日：2012-10-24

申请人： SOUTHEAST UNIVERSITY

发明人： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

IPC分类号： H01L27/24 ,  H01L29/739 ,  H01L29/40 ,  H01L27/12 ,  H01L29/06 ,  H01L27/06

CPC分类号： H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

摘要： A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

摘要翻译： 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

公开(公告)号：US20140203406A1

公开(公告)日：2014-07-24

申请号：US14240287

申请日：2012-08-14

申请人： SOUTHEAST UNIVERSITY

发明人： Longxing Shi ,  Qinsong Qian ,  Weifeng Sun ,  Jing Zhu ,  Xianguo Huang ,  Shengli Lu

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L21/761

CPC分类号： H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L21/823481 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7835

摘要： An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

摘要翻译： 高电压驱动电路的隔离结构包括P型衬底和P型外延层; 在P型外延层上布置有高电压区域，低电压区域和高低压端子区域; 在高低压区和低电压区之间设置第一P型结隔离区，高电压区与低压区之间设置高压绝缘栅场效应管; 高压绝缘栅场效应管的两侧和高压绝缘栅场效应管与高边区之间的隔离结构形成为第二P型结隔离区。

公开(公告)号：US12051742B1

公开(公告)日：2024-07-30

申请号：US18577714

申请日：2022-12-29

申请人： SOUTHEAST UNIVERSITY

发明人： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Jie Ma ,  Peigang Liu ,  Longxing Shi

IPC分类号： H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US12027516B1

公开(公告)日：2024-07-02

申请号：US18568277

申请日：2022-12-29

申请人： SOUTHEAST UNIVERSITY

发明人： Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Weifeng Sun ,  Mengli Liu ,  Yanfeng Ma ,  Longxing Shi

IPC分类号： H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L49/02

CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7787

摘要： A GaN power semiconductor device integrated with a self-feedback gate control structure comprises a substrate, a buffer layer, a channel layer and a barrier layer. A gate control area is formed by a first metal source electrode, a first P-type GaN cap layer, a first metal gate electrode, a first metal drain electrode, a second P-type GaN cap layer and a second metal gate electrode. An active working area is formed by the first metal source electrode, a third P-type GaN cap layer, a third metal gate electrode, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode. The overall gate leaking current of the device is regulated by the gate control area, the integration level is high, the parasitic effect is small, and the charge-storage effect can be effectively relieved, thus improving the threshold stability of the device.

公开(公告)号：US11367785B2

公开(公告)日：2022-06-21

申请号：US17606216

申请日：2020-03-31

申请人： SOUTHEAST UNIVERSITY

发明人： Jing Zhu ,  Ankang Li ,  Long Zhang ,  Weifeng Sun ,  Shengli Lu ,  Longxing Shi

IPC分类号： H01L29/73 ,  H01L29/739 ,  H01L29/10

摘要： A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

公开(公告)号：US11081967B2

公开(公告)日：2021-08-03

申请号：US16617508

申请日：2018-09-28

申请人： SOUTHEAST UNIVERSITY

发明人： Qinsong Qian ,  Shengyou Xu ,  Qi Liu ,  Weifeng Sun ,  Shengli Lu ,  Longxing Shi

IPC分类号： H02M3/335 ,  H02M1/08 ,  H02M1/00

摘要： The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.

公开(公告)号：US12107167B2

公开(公告)日：2024-10-01

申请号：US17762929

申请日：2021-01-20

申请人： SOUTHEAST UNIVERSITY

发明人： Siyang Liu ,  Weifeng Sun ,  Chi Zhang ,  Shuxuan Xin ,  Shen Li ,  Le Qian ,  Chen Ge ,  Longxing Shi

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/778 ,  H01L29/812

CPC分类号： H01L29/7851 ,  H01L29/1095 ,  H01L29/778 ,  H01L29/8122

摘要： The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

公开(公告)号：US12046990B1

公开(公告)日：2024-07-23

申请号：US18641384

申请日：2024-04-21

申请人： SOUTHEAST UNIVERSITY

发明人： Shen Xu ,  Haiqing Zhang ,  Yujie Liu ,  Ruizhi Wang ,  Yuan Gao ,  Yongjia Li ,  Weifeng Sun ,  Longxing Shi

IPC分类号： H02M1/08 ,  H02M1/00 ,  H02M3/158

CPC分类号： H02M1/082 ,  H02M1/0025 ,  H02M3/1586

摘要： A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.