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    FETs with Hybrid Channel Materials
    11.
    发明申请
    FETs with Hybrid Channel Materials 有权
    混合通道材料的FET

    公开(公告)号：US20130153964A1

    公开(公告)日：2013-06-20

    申请号：US13326825

    申请日：2011-12-15

    申请人： Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

    发明人： Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/8258 ,  H01L21/823807 ,  H01L27/0605

    摘要： Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

    摘要翻译： 提供在同一CMOS电路内采用不同通道材料的技术。 一方面，制造CMOS电路的方法包括以下步骤。 提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。 第一半导体层凹入第一有源区。 第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。 使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。 使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。

    Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
    12.
    发明申请
    Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation 审中-公开
    自对准III-V MOSFET制造，具有原位III-V外延和原位金属外延和接触形成

    公开(公告)号：US20120187505A1

    公开(公告)日：2012-07-26

    申请号：US13013206

    申请日：2011-01-25

    申请人： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

    发明人： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/8252 ,  H01L21/26546 ,  H01L21/28575 ,  H01L21/3245 ,  H01L29/0847 ,  H01L29/201 ,  H01L29/207 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66446 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/78

    摘要： A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.

    摘要翻译： 一种用于形成晶体管的方法，包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。 形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源/漏区上生长金属接触。 还公开了晶体管和计算机程序产品。

    Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact
    13.
    发明授权
    Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact 有权
    自对准III-V MOSFET扩散区和硅化物样合金接触

    公开(公告)号：US08822317B2

    公开(公告)日：2014-09-02

    申请号：US13603739

    申请日：2012-09-05

    申请人： Cheng-Wei Cheng ,  Augustin J. Hong ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu

    发明人： Cheng-Wei Cheng ,  Augustin J. Hong ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu

    IPC分类号： H01L21/336

    CPC分类号： H01L21/2258 ,  H01L21/246 ,  H01L21/28575 ,  H01L29/41775 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522

    摘要： A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.

    摘要翻译： 金属氧化物半导体场效应晶体管及其形成方法包括在与栅极叠层相邻的衬底上的曝光部分，在栅极堆叠上形成掺杂剂层，并在暴露并退火掺杂剂层驱动的部分中与衬底接触 掺杂到衬底中以在衬底中形成自对准掺杂剂区域。 去除掺杂剂层。 在栅极叠层上沉积含金属层，并在暴露部分与衬底接触。 对含金属层进行退火以将金属驱动到衬底中，以在掺杂区域内的衬底中形成的金属合金中形成自对准接触区域。 然后去除金属层。

    SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT
    14.
    发明申请
    SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT 有权
    自对准III-V MOSFET扩散区和类硅合金接触

    公开(公告)号：US20130001659A1

    公开(公告)日：2013-01-03

    申请号：US13603739

    申请日：2012-09-05

    申请人： Cheng-Wei Cheng ,  Augustin J. Hong ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu

    发明人： Cheng-Wei Cheng ,  Augustin J. Hong ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu

    IPC分类号： H01L29/78

    CPC分类号： H01L21/2258 ,  H01L21/246 ,  H01L21/28575 ,  H01L29/41775 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522

    摘要： A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.

    摘要翻译： 金属氧化物半导体场效应晶体管及其形成方法包括在与栅极叠层相邻的衬底上的曝光部分，在栅极叠层上形成掺杂剂层，并在暴露并退火掺杂剂层驱动的部分中与衬底接触 掺杂到衬底中以在衬底中形成自对准掺杂剂区域。 去除掺杂剂层。 在栅极叠层上沉积含金属层，并在暴露部分与衬底接触。 对含金属层进行退火以将金属驱动到衬底中，以在掺杂区域内的衬底中形成的金属合金中形成自对准接触区域。 然后去除金属层。

    Method for controlled removal of a semiconductor device layer from a base substrate
    16.
    发明授权
    Method for controlled removal of a semiconductor device layer from a base substrate 有权
    从基底基板控制去除半导体器件层的方法

    公开(公告)号：US09059073B2

    公开(公告)日：2015-06-16

    申请号：US13603944

    申请日：2012-09-05

    申请人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

    发明人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

    IPC分类号： H01L21/20 ,  H01L21/18 ,  H01L21/78 ,  H01L21/02 ,  H01L31/18

    CPC分类号： H01L21/187 ,  H01L21/02002 ,  H01L21/7813 ,  H01L31/1892 ,  Y02E10/50

    摘要： A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

    摘要翻译： 提供从基底基板去除半导体器件层的方法，其包括在基底基板的上表面上提供裂纹扩展层。 在裂纹扩展层上形成包括至少一个半导体器件的半导体器件层。 接下来，蚀刻裂纹扩展层的端部以在裂纹扩展层中引发裂纹。 蚀刻的裂纹扩展层然后被切割，以向半导体器件层的表面和另一个裂开的裂纹扩展层部分提供切割的裂纹扩展层部分到基底衬底的上表面。 从半导体器件层的表面去除切割的裂纹扩展层部分，并从基底基板的上表面除去另一个裂开的裂纹扩展层部分。

    HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE
    18.
    发明申请
    HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE 有权
    用于从单个基底衬底释放多个半导体器件层的高通量外延起升器

    公开(公告)号：US20130082303A1

    公开(公告)日：2013-04-04

    申请号：US13248792

    申请日：2011-09-29

    申请人： Cheng-Wei Cheng ,  Ning Li ,  Kuen-Ting Shiu

    发明人： Cheng-Wei Cheng ,  Ning Li ,  Kuen-Ting Shiu

    IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L29/12 ,  H01L21/20

    CPC分类号： H01L29/20 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/02507 ,  H01L21/30612 ,  H01L21/7813

    摘要： A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.

    摘要翻译： 包括牺牲材料层和半导体材料层的交替层的多层叠层形成在基底基板上。 堆叠的每个牺牲材料层的厚度从最靠近基底衬底形成的牺牲材料层向上增加。 由于这种厚度差异，每个牺牲材料层以不同的速率蚀刻，具有比较薄的牺牲材料层蚀刻更快的牺牲材料层。 执行蚀刻，其首先去除多层叠层的最厚牺牲材料层。 因此，首先释放多层堆叠内的最上层的半导体器件层。 随着蚀刻的继续，其余的牺牲材料层按照厚度减小的顺序被顺序地去除，并且其它半导体器件层被顺序地去除。

    High throughput epitaxial lift off for flexible electronics
    20.
    发明授权
    High throughput epitaxial lift off for flexible electronics 有权
    高通量外延剥离柔性电子元件

    公开(公告)号：US08541315B2

    公开(公告)日：2013-09-24

    申请号：US13236119

    申请日：2011-09-19

    申请人： Cheng-Wei Cheng ,  Kuen-Ting Shiu

    发明人： Cheng-Wei Cheng ,  Kuen-Ting Shiu

    IPC分类号： H01L21/302

    CPC分类号： H01L21/30604 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02439 ,  H01L21/02461 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/30612 ,  H01L21/7813

    摘要： A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.

    摘要翻译： 提供了从下面的基底基板去除半导体器件层的方法，其中在半导体器件层和基底衬底之间形成牺牲磷化物层。 在一些实施例中，半导体缓冲层可以在形成牺牲磷化物缓冲层之前形成在基底衬底的上表面上。 然后使用非HF蚀刻剂蚀刻所得到的结构，以从半导体衬底释放半导体器件层。 在从基底基板释放半导体器件层之后，可以重新使用基底衬底。