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    Method for Improving Design Window
    11.
    发明申请
    Method for Improving Design Window 审中-公开
    改进设计窗口的方法

    公开(公告)号：US20080237885A1

    公开(公告)日：2008-10-02

    申请号：US12134381

    申请日：2008-06-06

    申请人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

    发明人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

    IPC分类号： H01L23/48

    CPC分类号： H01L23/481 ,  G03F1/144 ,  G03F1/36 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

    摘要翻译： 提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。 用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。 该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的垂直导电特征图案中的每一个是否违反了设计规则。 如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。 然后形成照相掩模。 可以使用光掩膜形成半导体结构。

    Method for improving design window
    12.
    发明授权
    Method for improving design window 有权
    改善设计窗口的方法

    公开(公告)号：US07404167B2

    公开(公告)日：2008-07-22

    申请号：US11320513

    申请日：2005-12-27

    申请人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

    发明人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

    CPC分类号： H01L23/481 ,  G03F1/144 ,  G03F1/36 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

    摘要翻译： 提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。 用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。 该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。 如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。 然后形成照相掩模。 可以使用光掩膜形成半导体结构。

    SOLAR CELL AND SOLAR CELL MODULE
    13.
    发明申请
    SOLAR CELL AND SOLAR CELL MODULE 审中-公开
    太阳能电池和太阳能电池模块

    公开(公告)号：US20130104956A1

    公开(公告)日：2013-05-02

    申请号：US13493379

    申请日：2012-06-11

    申请人： Ming-Tzu Chou ,  Chien-Wen Chen ,  Ching-Hao Tu ,  Chih-Chiang Huang ,  Kang-Cheng Lin

    发明人： Ming-Tzu Chou ,  Chien-Wen Chen ,  Ching-Hao Tu ,  Chih-Chiang Huang ,  Kang-Cheng Lin

    IPC分类号： H01L31/05 ,  H01L31/0224

    CPC分类号： H01L31/022433 ,  H01L31/0504 ,  Y02E10/50

    摘要： A solar cell module includes multiple solar cells connected in series through wiring units. Each solar cell comprises an electrode unit disposed on a photoelectric conversion unit converting solar energy into electrical energy, and including multiple finger electrodes. At least one finger electrode has a first conducting section connected to a bus bar electrode, and a second conducting section disposed on one side of the first conducting section, extending away from the bus bar electrode and having a thickness greater than that of each of the first conducting section and the bus bar electrode.

    摘要翻译： 太阳能电池模块包括通过布线单元串联连接的多个太阳能电池。 每个太阳能电池包括设置在光电转换单元上的电极单元，其将太阳能转换成电能，并且包括多个指状电极。 至少一个指状电极具有连接到母线电极的第一导电部分和设置在第一导电部分的一侧上的第二导电部分，其远离母线电极延伸，并且具有大于 第一导电段和母线电极。

    Battery cell and electronic apparatus with electrostatic discharge protection
    14.
    发明授权
    Battery cell and electronic apparatus with electrostatic discharge protection 失效
    具有静电放电保护的电池和电子设备

    公开(公告)号：US08284537B2

    公开(公告)日：2012-10-09

    申请号：US12849201

    申请日：2010-08-03

    申请人： Chien-Wen Chen

    发明人： Chien-Wen Chen

    IPC分类号： H05F3/02

    CPC分类号： H05K1/0259 ,  H05K2201/10037 ,  H05K2201/10969

    摘要： An electronic apparatus with electrostatic discharge protection includes: a conducting casing and a circuit board. The circuit board has a power ground node and a conditional conducting path, and is set inside the conducting casing. The conditional conducting path further includes: a conducting element and an electrostatic discharging component. One end of the conducting element is electrically connected to the conducting casing, and the electrostatic discharging component is electrically connected between another end of the conducting element and the power ground node. When the voltage variation between the two ends of the electrostatic discharging element reaches a preset condition, the electrostatic discharging component functions as a short circuit; otherwise, the electrostatic discharging element is equivalent to a high impedance element. The power ground node electrically connects to an electrode of a battery for using it as a vessel of receiving electrostatic charges.

    摘要翻译： 具有静电放电保护的电子设备包括：导电壳体和电路板。 电路板具有电源接地节点和条件导电路径，并设置在导电壳体的内部。 条件导电路径还包括：导电元件和静电放电元件。 导电元件的一端电连接到导电壳体，静电放电元件电连接在导电元件的另一端与电源接地节点之间。 当静电放电元件的两端之间的电压变化达到预设状态时，静电​​放电元件用作短路; 否则，静电放电元件相当于高阻抗元件。 电源接地节点电连接到电池的电极，以将其用作接收静电电荷的容器。

    METHOD, SYSTEM, APPARATUS AND COMPUTER-READABLE MEDIUM FOR BROWSING SPOT INFORMATION
    15.
    发明申请
    METHOD, SYSTEM, APPARATUS AND COMPUTER-READABLE MEDIUM FOR BROWSING SPOT INFORMATION 有权
    方法，系统，设备和计算机可读介质，用于浏览SPOT信息

    公开(公告)号：US20120059576A1

    公开(公告)日：2012-03-08

    申请号：US13039314

    申请日：2011-03-03

    申请人： Po-Yen Lee ,  Chien-Wen Chen ,  Pai-Chang Yeh ,  Li-Wen Lian

    发明人： Po-Yen Lee ,  Chien-Wen Chen ,  Pai-Chang Yeh ,  Li-Wen Lian

    IPC分类号： G06F3/048 ,  G01C21/00

    CPC分类号： G06F3/04842 ,  G01C21/00 ,  G01C21/3682 ,  G09B29/007

    摘要： A method, a system, an apparatus, and a computer-readable medium for browsing spot information, adapted to an electronic device, are provided. In the present method, a plurality of spot information are retrieved, in which each of the spot information at least comprises a picture and a location of a spot. Next, an electronic map is displayed and a spot marker is marked at the spot location of each spot information on the electronic map. Meanwhile, a spot browsing bar is displayed on a side of the electronic map and the spot pictures of the spot information are sequentially displayed in the spot browsing bar. When a select operation of a certain spot marker on the electronic map is received, the spot browsing bar is scrolled to show the spot picture corresponding to the selected spot marker.

    摘要翻译： 提供了适用于电子设备的用于浏览点信息的方法，系统，装置和计算机可读介质。 在本方法中，检索多个点信息，其中每个点信息至少包括图片和点的位置。 接下来，显示电子地图，并且在电子地图上的每个点信息的点位置处标记点标记。 同时，在电子地图的一侧显示现场浏览栏，并且在点浏览栏中顺序地显示点信息的照片。 当接收到电子地图上的特定点标记的选择操作时，滚动显示浏览栏以显示与所选择的点标记对应的点图。

    SYSTEMS AND METHODS FOR INTERFACE MANAGEMENT
    18.
    发明申请
    SYSTEMS AND METHODS FOR INTERFACE MANAGEMENT 审中-公开
    用于界面管理的系统和方法

    公开(公告)号：US20110258555A1

    公开(公告)日：2011-10-20

    申请号：US13086118

    申请日：2011-04-13

    申请人： Po-Yen LEE ,  Pai-Chang Yeh ,  Chien-Wen Chen ,  Li-Wen Lian

    发明人： Po-Yen LEE ,  Pai-Chang Yeh ,  Chien-Wen Chen ,  Li-Wen Lian

    IPC分类号： G06F3/01 ,  G06F15/16

    CPC分类号： G06Q10/00 ,  G06F9/451

    摘要： Methods and systems for interface management are provided. First, a request message, requesting for arrangement information of at least one interface is received from a server, wherein the at least one interface contains at least one object and can be displayed on a screen of an electronic device according to the arrangement information. In response to the request message, respective arrangement information of the at least one interface is obtained and then transmitted to the server, such that a simulated interface of the at least one interface is displayed on a user interface at the server side based on the respective arrangement information received by the server, wherein when a change is made to the simulated interface of the at least one interface at the server side, the arrangement of the at least one interface is accordingly changed.

    摘要翻译： 提供了接口管理的方法和系统。 首先，从服务器接收请求消息至少一个接口的配置信息的请求消息，其中，所述至少一个接口包含至少一个对象，并且可以根据所述配置信息显示在电子设备的屏幕上。 响应于请求消息，获得至少一个接口的各自的配置信息，然后发送到服务器，使得至少一个接口的模拟接口基于相应的在服务器侧的用户接口上显示 由所述服务器接收的配置信息，其中当对所述服务器侧的所述至少一个接口的所述模拟接口进行改变时，所述至少一个接口的配置相应地改变。

    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
    19.
    发明申请
    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
    超大型集成电路的精确寄生电容提取

    公开(公告)号：US20110023003A1

    公开(公告)日：2011-01-27

    申请号：US12893870

    申请日：2010-09-29

    申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

    摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

    Accurate parasitic capacitance extraction for ultra large scale integrated circuits
    20.
    发明授权
    Accurate parasitic capacitance extraction for ultra large scale integrated circuits 有权
    超大规模集成电路的精确寄生电容提取

    公开(公告)号：US07818698B2

    公开(公告)日：2010-10-19

    申请号：US11865304

    申请日：2007-10-01

    申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

    摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。