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    Methods to form memory devices having a capacitor with a recessed electrode
    11.
    发明授权
    Methods to form memory devices having a capacitor with a recessed electrode 有权
    形成具有带有凹陷电极的电容器的存储器件的方法

    公开(公告)号：US08441097B2

    公开(公告)日：2013-05-14

    申请号：US12646957

    申请日：2009-12-23

    申请人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

    发明人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

    IPC分类号： H01L21/02

    CPC分类号： H01L28/90 ,  H01L27/0733

    摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

    摘要翻译： 描述形成具有凹陷电极的MIM电容器的存储器件的方法。 在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。 该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。 该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。 该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

    METHODS TO FORM MEMORY DEVICES HAVING A CAPACITOR WITH A RECESSED ELECTRODE
    12.
    发明申请
    METHODS TO FORM MEMORY DEVICES HAVING A CAPACITOR WITH A RECESSED ELECTRODE 有权
    用于形成具有电容器的电容器的存储器件的方法

    公开(公告)号：US20110147888A1

    公开(公告)日：2011-06-23

    申请号：US12646957

    申请日：2009-12-23

    申请人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

    发明人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/90 ,  H01L27/0733

    摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

    摘要翻译： 描述形成具有凹陷电极的MIM电容器的存储器件的方法。 在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。 该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。 该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。 该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

    Vertical meander inductor for small core voltage regulators
    16.
    发明授权
    Vertical meander inductor for small core voltage regulators 有权
    用于小型电压调节器的垂直弯曲电感器

    公开(公告)号：US09129844B2

    公开(公告)日：2015-09-08

    申请号：US14319429

    申请日：2014-06-30

    申请人： Christopher J. Jezewski ,  Kevin P. O'Brien

    发明人： Christopher J. Jezewski ,  Kevin P. O'Brien

    IPC分类号： H01L49/02 ,  H01L21/48 ,  H01L23/64 ,  H01L23/522

    CPC分类号： H01L28/10 ,  H01L21/4814 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

    摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。 例如，半导体管芯包括衬底。 集成电路设置在基板的有源表面上。 电感器耦合到集成电路。 电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。 绝缘层具有起伏的形貌。

    Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
    18.
    发明授权
    Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches 有权
    通过交替的凹槽形成高密度，高短路裕度和低电容互连的方法

    公开(公告)号：US09054164B1

    公开(公告)日：2015-06-09

    申请号：US14139363

    申请日：2013-12-23

    申请人： Christopher J. Jezewski ,  Jasmeet S. Chawla

    发明人： Christopher J. Jezewski ,  Jasmeet S. Chawla

    IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/528 ,  H01L21/02126 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

    摘要翻译： 本发明的实施例描述了用于半导体器件的低电容互连结构以及用于制造这种器件的方法。 根据本发明的实施例，低电容互连结构包括层间电介质（ILD）。 第一和第二互连线以交替图案设置在ILD中。 第一互连线的顶表面可以在第二互连线的顶表面下方凹入。 第一互连线的凹槽中的增加减小相邻互连之间的线间电容。 另外的实施例包括利用不同的介电材料作为第一和第二互连线之上的蚀刻帽。 在蚀刻过程中，不同的材料可能具有彼此高的选择性。 因此，增加了对各个互连线的接触的对准预算。

    PLATEABLE DIFFUSION BARRIER TECHNIQUES
    19.
    发明申请
    PLATEABLE DIFFUSION BARRIER TECHNIQUES 审中-公开
    可扩展扩展障碍技术

    公开(公告)号：US20140019716A1

    公开(公告)日：2014-01-16

    申请号：US13545910

    申请日：2012-07-10

    申请人： Christopher J. Jezewski

    发明人： Christopher J. Jezewski

    IPC分类号： H01L23/532 ,  G06F15/76 ,  G06F9/02 ,  H01L21/768

    CPC分类号： H01L23/53252 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are disclosed for forming a directly plateable diffusion barrier within an interconnect structure to prevent diffusion of interconnect fill metal into surrounding dielectric material and lower metal layers. The barrier can be used in back-end interconnect metallization processes and, in an embodiment, renders a seed layer unnecessary. In accordance with various example embodiments, the barrier can be implemented, for instance, as: (1) a single layer of ruthenium silicide (RuSix) or ruthenium silicide nitride (RuSixNy); (2) a bi-layer of Ru/RuSix, RuSix/Ru, Ru/RuSixNy, or RuSixNy/Ru; or (3) a tri-layer of Ru/RuSix/Ru or Ru/RuSixNy/Ru. In some embodiments, Si and/or N concentrations can be adjusted to alter the barrier's degree of diffusion protection, receptiveness to the fill metal, and/or electrical conductivity.

    摘要翻译： 公开了用于在互连结构内形成直接平板化扩散阻挡层的技术，以防止互连填充金属扩散到周围的电介质材料和下层金属层。 阻挡层可以用于后端互连金属化工艺中，并且在一个实施例中使得不需要种子层。 根据各种示例性实施例，阻挡层可以例如如下实现：（1）单层钌硅化物（RuSix）或氮化钌氮化物（RuSixNy）; （2）Ru / RuSix，RuSix / Ru，Ru / RuSixNy或RuSixNy / Ru的双层; 或（3）Ru / RuSix / Ru或Ru / RuSixNy / Ru三层。 在一些实施方案中，可以调节Si和/或N浓度以改变屏障的扩散保护程度，对填充金属的接受性和/或导电性。

    SPUTTER DEPOSITION OF METAL ALLOY TARGETS CONTAINING A HIGH VAPOR PRESSURE COMPONENT
    20.
    发明申请
    SPUTTER DEPOSITION OF METAL ALLOY TARGETS CONTAINING A HIGH VAPOR PRESSURE COMPONENT 审中-公开
    含有高蒸汽压力组分的金属合金靶材的溅射沉积

    公开(公告)号：US20090166181A1

    公开(公告)日：2009-07-02

    申请号：US11968131

    申请日：2007-12-31

    申请人： Christopher J. Jezewski ,  Juan Dominguez

    发明人： Christopher J. Jezewski ,  Juan Dominguez

    IPC分类号： C23C14/34 ,  C23C14/56

    CPC分类号： C23C14/3414 ,  H01L21/2855

    摘要： Compositions and methods for enabling sputter deposition from targets containing high vapor pressure compounds are describe. An element or compound with a high vapor pressure may be combined with an element or compound with a lower vapor pressure to form a low vapor pressure compound. An alloy sputtering target may then be formed by combining the low vapor pressure compound with a metal that serves as the main material of the sputter target. In some instances, the low vapor pressure compound may comprise MgB2, MgB4, or MgB7. Additionally, the metal that serves as the main material of the sputter target may comprise copper. As a result, the alloy target may comprise Cu(MgB2), Cu(MgB4), or Cu(MgB7). Other embodiments are also described.

    摘要翻译： 描述了能够从含有高蒸气压化合物的靶溅射沉积的组合物和方法。 具有高蒸气压的元素或化合物可与具有较低蒸气压的元素或化合物组合以形成低蒸气压化合物。 然后可以通过将低蒸气压化合物与用作溅射靶的主要材料的金属组合来形成合金溅射靶。 在一些情况下，低蒸汽压化合物可以包含MgB 2，MgB 4或MgB 7。 另外，用作溅射靶的主要材料的金属可以包括铜。 结果，合金靶可以包含Cu（MgB 2），Cu（MgB 4）或Cu（MgB 7）。 还描述了其它实施例。