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    Method for making a semiconductor device having increased conductive material reliability
    3.
    发明授权
    Method for making a semiconductor device having increased conductive material reliability 有权
    制造具有增加的导电材料可靠性的半导体器件的方法

    公开(公告)号：US07229922B2

    公开(公告)日：2007-06-12

    申请号：US10695249

    申请日：2003-10-27

    申请人： Valery M. Dubin ,  Ramanan V. Chebiam

    发明人： Valery M. Dubin ,  Ramanan V. Chebiam

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

    摘要翻译： 描述了具有导电材料可靠性增加的半导体器件的半导体器件的方法和装置。 该方法和装置包括在衬底上形成导电路径。 由第一材料制成的导电路径。 然后将第二材料沉积在导电路径上。 一旦第二材料沉积在导电路径上，则促进了第二材料进入导电路径的扩散。 第二材料具有预定的溶解度以基本上扩散到第一材料内的晶界。

    SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME
    5.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME 有权
    具有用于嵌入式动态随机存取存储器（EDRAM）的集成四元组电容器的半导体结构及其形成方法

    公开(公告)号：US20120326274A1

    公开(公告)日：2012-12-27

    申请号：US13165615

    申请日：2011-06-21

    申请人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    发明人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    IPC分类号： H01L29/92 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L27/10894 ,  H01L28/91

    摘要： Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.

    摘要翻译： 描述了具有用于eDRAM的集成四足壁电容器的半导体结构及其形成方法。 例如，嵌入式四壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。 沟槽有一个底部和侧壁。 金属板的四重布置设置在沟槽的底部，与侧壁间隔开。 第二电介质层设置在沟槽的侧壁和金属板的四重布置上。 顶部金属板层设置在第二介电层上并与第二介质层保形。

    Conformal electroless deposition of barrier layer materials
    6.
    发明授权
    Conformal electroless deposition of barrier layer materials 有权
    阻挡层材料的保形无电沉积

    公开(公告)号：US07629252B2

    公开(公告)日：2009-12-08

    申请号：US11318137

    申请日：2005-12-23

    申请人： Kevin P. O'Brien ,  Chin-Chang Cheng ,  Ramanan V. Chebiam ,  Valery M. Dubin ,  Sridhar Balakrishnan

    发明人： Kevin P. O'Brien ,  Chin-Chang Cheng ,  Ramanan V. Chebiam ,  Valery M. Dubin ,  Sridhar Balakrishnan

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  B82Y30/00 ,  H01L21/288 ,  H01L21/76874

    摘要： Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.

    摘要翻译： 使用利用与催化金属复合的偶联剂和由此形成的结构的化学沉积技术形成的阻挡材料层来制造互连结构的方法。 该制造基本上包括提供介电材料层，其具有从其第一表面延伸到电介质材料中的开口，将该耦合剂粘合到该开口内的电介质材料，以及无电沉积阻挡材料层，其中该无电沉积阻挡材料层 材料粘附到偶联剂的催化金属上。

    Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same
    8.
    发明授权
    Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same 有权
    具有用于嵌入式动态随机存取存储器（eDRAM）的集成四足壁电容器的半导体结构及其形成方法

    公开(公告)号：US08519510B2

    公开(公告)日：2013-08-27

    申请号：US13165615

    申请日：2011-06-21

    申请人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    发明人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    IPC分类号： H01L29/92

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L27/10894 ,  H01L28/91

    摘要： Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.

    摘要翻译： 描述了具有用于eDRAM的集成四足壁电容器的半导体结构及其形成方法。 例如，嵌入式四壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。 沟槽有一个底部和侧壁。 金属板的四重布置设置在沟槽的底部，与侧壁间隔开。 第二电介质层设置在沟槽的侧壁和金属板的四重布置上。 顶部金属板层设置在第二介电层上并与第二介质层保形。

    Method for making a semiconductor device having increased conductive material reliability
    9.
    发明授权
    Method for making a semiconductor device having increased conductive material reliability 有权
    制造具有增加的导电材料可靠性的半导体器件的方法

    公开(公告)号：US07372165B2

    公开(公告)日：2008-05-13

    申请号：US11077252

    申请日：2005-03-09

    申请人： Valery M. Dubin ,  Ramanan V. Chebiam

    发明人： Valery M. Dubin ,  Ramanan V. Chebiam

    IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

    摘要翻译： 描述了具有导电材料可靠性增加的半导体器件的半导体器件的方法和装置。 该方法和装置包括在衬底上形成导电路径。 由第一材料制成的导电路径。 然后将第二材料沉积在导电路径上。 一旦第二材料沉积在导电路径上，则促进了第二材料进入导电路径的扩散。 第二材料具有预定的溶解度以基本上扩散到第一材料内的晶界。