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公开(公告)号：US5307007A
公开(公告)日：1994-04-26
申请号：US963093
申请日：1992-10-19
Applicant: Chung-Yu Wu , Shu-Yuan Chin
Inventor： Chung-Yu Wu , Shu-Yuan Chin
Abstract: Precise CMOS bandgap voltage and current references which uses the difference of MOS source-gate voltages to perform efficient curvature compensation are proposed and analyzed. Applying the developed design strategies, bandgap voltage references (BVR) with a temperature drift below 10 ppm/.degree.C. and a power supply drift below 10 ppm/V can be realized. For bandgap current references, both drifts can be under 15 ppm. An experimental BVR chip shows an average drift of 5.5 ppm/.degree.C. from -60.degree. C. to 150.degree. C. and 25 .mu.V/V for supply voltages between 5 V and 15 V at 25.degree. C. Due to novel curvature compensation, the circuit structure of the proposed references is simple and both chip area and power consumption are small.
Abstract translation: 提出并分析了精确的CMOS带隙电压和电流参考，其使用MOS源极栅极电压的差异来执行有效的曲率补偿。 应用开发的设计策略，温度漂移低于10 ppm /℃的带隙电压基准（BVR）。 并且可以实现低于10ppm / V的电源漂移。 对于带隙电流参考，两个漂移都可以在15 ppm以下。 实验性BVR芯片显示出5.5ppm /℃的平均漂移。 从-60摄氏度到150摄氏度和25摄氏度（V / V），电源电压在25摄氏度在25摄氏度之间。由于新的曲率补偿，所提出的参考文献的电路结构简单， 芯片面积和功耗都很小。
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公开(公告)号：US07215370B2
公开(公告)日：2007-05-08
申请号：US10624517
申请日：2003-07-23
Applicant: Cheng-Ta Chiang , Chung-Yu Wu
Inventor： Cheng-Ta Chiang , Chung-Yu Wu
CPC classification number: H04N5/3745 , H04N5/23241 , H04N5/357 , H04N5/376
Abstract: A Pseudo Bipolar Junction Transistor(Pseudo-BJT) based retinal focal-plane sensing system is an instant image sensing and front-end processing system with the advantages of high dynamic range and instant image processing. In addition, the system proposes a Pseudo-BJT based retinal focal-plane sensor with adaptive current Schmitt trigger and smoothing network for applying a new Pseudo-BJT circuit structure to mimic parts of functions of the cells in the outer plexiform layer of the real retina. It is suitable to resolve the existing technical drawbacks performing major functions in optical image detecting circuits, such as image recognition, image tracing, robot vision, bar-code/character readers, etc.
Abstract translation: 一种基于伪双极结晶体管（Pseudo-BJT）的视网膜焦平面感测系统是具有动态范围高，瞬时图像处理优势的即时图像感知和前端处理系统。 此外，该系统提出了一种基于Pseudo-BJT的视网膜焦平面传感器，具有自适应电流施密特触发和平滑网络，用于应用新的伪BJT电路结构，以模拟实际视网膜的外丛状层中的细胞功能的一部分 。 适合解决在图像识别，图像追踪，机器人视觉，条形码/字符读取器等光学图像检测电路中执行主要功能的现有技术缺陷。
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公开(公告)号：US20050018062A1
公开(公告)日：2005-01-27
申请号：US10624517
申请日：2003-07-23
Applicant: Cheng-Ta Chiang , Chung-Yu Wu
Inventor： Cheng-Ta Chiang , Chung-Yu Wu
CPC classification number: H04N5/3745 , H04N5/23241 , H04N5/357 , H04N5/376
Abstract: A Pseudo Bipolar Junction Transistor(Pseudo-BJT) based retinal focal-plane sensing system is an instant image sensing and front-end processing system with the advantages of high dynamic range and instant image processing. In addition, the system proposes a Pseudo-BJT based retinal focal-plane sensor with adaptive current Schmitt trigger and smoothing network for applying a new Pseudo-BJT circuit structure to mimic parts of functions of the cells in the outer plexiform layer of the real retina. It is suitable to resolve the existing technical drawbacks performing major functions in optical image detecting circuits, such as image recognition, image tracing, robot vision, bar-code/character readers, etc.
Abstract translation: 一种基于伪双极结晶体管（Pseudo-BJT）的视网膜焦平面感测系统是具有动态范围高，瞬时图像处理优势的即时图像感知和前端处理系统。 此外，该系统提出了一种基于Pseudo-BJT的视网膜焦平面传感器，具有自适应电流施密特触发和平滑网络，用于应用新的伪BJT电路结构，以模拟实际视网膜的外丛状层中的细胞功能的一部分 。 适合解决在图像识别，图像追踪，机器人视觉，条形码/字符读取器等光学图像检测电路中执行主要功能的现有技术缺陷。
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公开(公告)号：US5838050A
公开(公告)日：1998-11-17
申请号：US932010
申请日：1997-09-17
Applicant: Ming-Dou Ker , Chung-Yu Wu , Chien-Chang Huang , Chau-Neng Wu , Ta-Lee Yu
Inventor： Ming-Dou Ker , Chung-Yu Wu , Chien-Chang Huang , Chau-Neng Wu , Ta-Lee Yu
IPC: H01L27/02 , H01L27/092 , H01L27/72
CPC classification number: H01L27/0251 , H01L27/092
Abstract: A CMOS device containing a plurality of hexagon cells over a semiconductor substrate is disclosed. Each hexagon cell includes a hexagonal ring gate, a drain diffusion region and a source diffusion region. The hexagonal ring gate is made of conducting materials and a dielectric layer over the substrate, therefore defining a channel region in the substrate between the gate and the substrate. The entire drain diffusion region in the substrate is enclosed by the hexagonal ring gate. The source diffusion region surrounds the hexagonal ring gate in the substrate. Each hexagon cell further provides a drain contact in the center of the drain diffusion region. A plurality of source contacts are arranged around the ring gate over the substrate. The hexagon cells of a unique hexagon device are surrounded by a first guard ring and a second guard ring. The hexagon device can be used as a CMOS output buffer or input ESD protection circuit to reduce the layout area of an integrated circuit.
Abstract translation: 公开了一种在半导体衬底上包含多个六边形单元的CMOS器件。 每个六边形单元包括六边形环形栅极，漏极扩散区域和源极扩散区域。 六角环形栅极由导电材料和介质层构成，因此在栅极和衬底之间在衬底中限定沟道区。 衬底中的整个漏极扩散区域被六边形环形栅极包围。 源极扩散区域围绕衬底中的六角形环形栅极。 每个六边形单元还在漏极扩散区域的中心处提供漏极接触。 在环形栅极周围多个源极触点布置在衬底上。 独特的六边形装置的六边形单元被第一保护环和第二保护环包围。 六边形器件可用作CMOS输出缓冲器或输入ESD保护电路，以减少集成电路的布局面积。
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公开(公告)号：US5714784A
公开(公告)日：1998-02-03
申请号：US545286
申请日：1995-10-19
Applicant: Ming-Dou Ker , Chung-Yu Wu , Chien-Chang Huang , Chau-Neng Wu , Ta-Lee Yu
Inventor： Ming-Dou Ker , Chung-Yu Wu , Chien-Chang Huang , Chau-Neng Wu , Ta-Lee Yu
IPC: H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L23/62 , H01L29/76
CPC classification number: H01L29/1087 , H01L27/0251 , H01L29/0692 , H01L29/0847 , H01L29/4238 , H01L2924/0002
Abstract: The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.
Abstract translation: 本发明是电子器件，特别是MOS晶体管。 使用方形布局样式来实现MOS器件。 通过使用当前的布局方式，输出缓冲器的输出驱动/吸收能力以及输出缓冲器或输入ESD保护电路中的NMOS和PMOS器件的ESD保护能力在较小的布局区域内得到显着改善。 通过这种正方形布局，输出节点处的漏极扩散面积和漏极到体积寄生电容都减小了。 使用本布局样式的设备可以组装成更大的矩形（或方形）和类似功能的设备。 因此，目前的方形布局样式对于亚微米CMOS VLSI / ULSI在高密度和高速应用中非常有吸引力。
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Patent Agency Ranking
公开(公告)号：US5592114A
公开(公告)日：1997-01-07
申请号：US275172
申请日：1994-07-14
Applicant: Chung-Yu Wu , Shu-Yuan Chin
Inventor： Chung-Yu Wu , Shu-Yuan Chin
IPC: H03K19/096 , H03K3/353
CPC classification number: H03K19/0963
Abstract: A true type single-phase shift circuit including a pair of PMOS transistors, a pair of NMOS transistors, a pair of first-type MOS transistors and one second-type transistor. The source terminals of the two PMOS transistors are both coupled to a first electric potential, the gate terminal of one PMOS transistor is coupled to a data signal, and the gate terminal of the second PMOS transistor is connected between the two first-type MOS transistors. The source terminals of the two NMOS transistors are both coupled to a second electric potential; the gate terminal of one NMOS transitors is coupled to the data signal and the gate of the second NMOS transistor is connected between the two first-type MOS transistors. The two first type MOS transistors are serially connected between the drain terminals of one of the two PMOS transistors and the drain terminal of one of the two NMOS transistors. Each gate terminal of the two first type MOS transistors is coupled to a clock pulse signal. The second-type MOS transistor is serially connected between the drain terminal of the other PMOS transistor and the drain terminal of the other NMOS transistor. The gate terminal of the second type MOS transistor is coupled with the clock pulse signal and its drain terminal is used as an output terminal.
Abstract translation: 一种真正型单相移相电路，包括一对PMOS晶体管，一对NMOS晶体管，一对第一型MOS晶体管和一个第二型晶体管。 两个PMOS晶体管的源极端子都耦合到第一电位，一个PMOS晶体管的栅极端子耦合到数据信号，并且第二PMOS晶体管的栅极端子连接在两个第一型MOS晶体管 。 两个NMOS晶体管的源极端子都耦合到第二电位; 一个NMOS运算器的栅极端子耦合到数据信号，第二NMOS晶体管的栅极连接在两个第一型MOS晶体管之间。 两个第一类型MOS晶体管串联连接在两个PMOS晶体管之一的漏极端子和两个NMOS晶体管之一的漏极端子之间。 两个第一类型MOS晶体管的每个栅极端子耦合到时钟脉冲信号。 第二型MOS晶体管串联连接在另一个PMOS晶体管的漏极端子和另一个NMOS晶体管的漏极端子之间。 第二型MOS晶体管的栅极端子与时钟脉冲信号耦合，其漏极端子用作输出端子。
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公开(公告)号：US5473169A
公开(公告)日：1995-12-05
申请号：US406170
申请日：1995-03-17
Applicant: Ming-Dou Ker , Chung-Yu Wu , Chung-Yuan Lee , Joe Ko
Inventor： Ming-Dou Ker , Chung-Yu Wu , Chung-Yuan Lee , Joe Ko
CPC classification number: H01L27/0259
Abstract: A complementary-SCR electrostatic discharge protection circuit in a silicon substrate, coupling to I/O pads for bypassing electrostatic current of positive or negative polarity respect to power supply voltages V.sub.DD and V.sub.SS. The circuit comprises a first SCR and a second SCR each having an anode, a cathode, an anode gate and a cathode gate. The circuit of the present invention preferably includes a finger type layout structure for providing a larger capacity to bypass electrostatic current. It is also characterized by a base-emitter shorting design to avoid a V.sub.DD -to-V.sub.SS latch-up effect.
Abstract translation: 在硅衬底中的互补SCR静电放电保护电路，耦合到I / O焊盘，用于绕过电源电压VDD和VSS旁路正极或负极性的静电电流。 电路包括第一SCR和第二SCR，每个具有阳极，阴极，阳极栅极和阴极栅极。 本发明的电路优选地包括用于提供更大容量来绕过静电电流的手指型布局结构。 它还具有基极 - 发射极短路设计的特征，以避免VDD至VSS闭锁效应。
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18.发明授权
公开(公告)号：US5168461A
公开(公告)日：1992-12-01
申请号：US396596
申请日：1989-08-21
Applicant: Chung-Yu Wu , Tsai-Chung Yu
Inventor： Chung-Yu Wu , Tsai-Chung Yu
CPC classification number: G06G7/1865 , H03H19/002
Abstract: Backward-mapping switched capacitor (SC) differentiators for MOS technology integrated circuit implementation, as well as forward mapping (FM) and bilinear-mapping (BIM) SC differentiators, are disclosed. The SC differentiator is employed in filters either alone or in combination with SC integrators. The filters include biquads, ladder filters, FIR filters, IIR filters and N-path filters.A fully differential operational amplifier with high and symmetrical driving capability is also described.
Abstract translation: 公开了用于MOS技术集成电路实现的反向映射开关电容器（SC）微分器以及前向映射（FM）和双线性映射（BIM）SC微分器。 SC微分器单独使用或与SC积分器组合使用在滤波器中。 滤波器包括双二阶梯，梯形滤波器，FIR滤波器，IIR滤波器和N路径滤波器。 还描述了具有高和对称驱动能力的全差分运算放大器。
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19.发明授权Sigma-delta analog-to-digital converters based on switched-capacitor differentiators and delays 失效基于开关电容微分器和延迟的Sigma-delta模数转换器
公开(公告)号：US5140325A
公开(公告)日：1992-08-18
申请号：US699893
申请日：1991-05-14
Applicant: Tsai-Chung Yu , Yie-Yuan Shien , Chung-Yu Wu , Tung-Kwan Lin
Inventor： Tsai-Chung Yu , Yie-Yuan Shien , Chung-Yu Wu , Tung-Kwan Lin
Abstract: Sigma-delta analog to digital converters based upon switched capacitor delay and switched capacitor differentiator circuits are described. These switched capacitor circuits have the advantages that they are less sensitive to clock feed-through noise, dc offset voltage and power supply voltage, etc. Design examples of one-bit second-order sigma-delta analog digital converter are given to substantiate both design methodology, circuit features and the utility of these new circuit structures.
Abstract translation: 描述了基于开关电容器延迟和开关电容微分电路的Σ-Δ模数转换器。 这些开关电容器电路具有的优点是它们对时钟馈通噪声，直流失调电压和电源电压等不太敏感。一位二阶Σ-Δ模拟数字转换器的设计实例被赋予两个设计 方法，电路特征以及这些新电路结构的实用性。
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公开(公告)号：US08264290B2
公开(公告)日：2012-09-11
申请号：US12805572
申请日：2010-08-06
Applicant: Zue-Der Huang , Chung-Yu Wu
Inventor： Zue-Der Huang , Chung-Yu Wu
IPC: H03B5/12
CPC classification number: H03B5/1228 , H03B5/1215 , H03B5/1218 , H03B5/1221 , H03B5/124 , H03B2200/0008
Abstract: A dual positive-feedbacks voltage controlled oscillator includes an oscillation circuit and a cross coupled pair circuit. The oscillation circuit includes a first transistor, a second transistor, an inductor and a plurality of capacitors. The gates of the first and second transistors are opposite to each other and coupled to two points of the inductor. The inductor and the capacitors are formed as a LC tank. The cross coupled pair circuit includes a third transistor and a fourth transistor. The gates of the third and fourth transistors are cross coupled to two points of the inductor. Thereby, the gate of the third transistor is coupled to the gate of the second transistor; the gate of the fourth transistor is coupled to the gate of the first transistor; the drain of the third transistor is coupled to the source of the first transistor; and the drain of the fourth transistor is coupled to the source of the second transistor.
Abstract translation: 双正压电压振荡器包括振荡电路和交叉耦合对电路。 振荡电路包括第一晶体管，第二晶体管，电感器和多个电容器。 第一和第二晶体管的栅极彼此相对并耦合到电感器的两个点。 电感器和电容器形成为LC箱。 交叉耦合对电路包括第三晶体管和第四晶体管。 第三和第四晶体管的栅极交叉耦合到电感器的两个点。 由此，第三晶体管的栅极耦合到第二晶体管的栅极; 第四晶体管的栅极耦合到第一晶体管的栅极; 第三晶体管的漏极耦合到第一晶体管的源极; 并且第四晶体管的漏极耦合到第二晶体管的源极。
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