公开(公告)号：US20200177167A1

公开(公告)日：2020-06-04

申请号：US16784392

申请日：2020-02-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jing BAI ,  Tejasvi DAS ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI

IPC: H03K3/01 ,  H03K17/687

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

公开(公告)号：US20200036352A1

公开(公告)日：2020-01-30

申请号：US16181762

申请日：2018-11-06

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Lei ZHU ,  Tejasvi DAS ,  John L. MELANSON ,  Wai-shun Wilson SHUM ,  Jing BAI ,  Xin ZHAO ,  Xiaofan FEI

IPC: H03G3/30 ,  H03F3/217 ,  H03F3/187 ,  H03F3/387

Abstract: A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

公开(公告)号：US20190260377A1

公开(公告)日：2019-08-22

申请号：US16162960

申请日：2018-10-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jing BAI ,  Tejasvi DAS ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI

IPC: H03K17/687 ,  H03K17/06 ,  G06F3/01

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

公开(公告)号：US20190115886A1

公开(公告)日：2019-04-18

申请号：US16133045

申请日：2018-09-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Alan Mark MORTON ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI ,  Johann G. GABORIAU ,  John L. MELANSON ,  Amar VELLANKI

IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00

Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

公开(公告)号：US20180212569A1

公开(公告)日：2018-07-26

申请号：US15622722

申请日：2017-06-14

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Lei ZHU ,  Ku HE ,  Xin ZHAO ,  Miao SONG ,  Saurabh SINGH ,  Vinod JAYAKUMAR

IPC: H03F1/02 ,  H03F3/217 ,  H03F3/21 ,  H03F3/183

CPC classification number: H03F1/0205 ,  H03F1/30 ,  H03F1/3264 ,  H03F3/183 ,  H03F3/187 ,  H03F3/21 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2200/03 ,  H03F2200/375 ,  H03F2203/45048

Abstract: A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

公开(公告)号：US20240187205A1

公开(公告)日：2024-06-06

申请号：US18471856

申请日：2023-09-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jeffrey SKARZYNSKI ,  Wai-Shun SHUM ,  Amar VELLANKI ,  Venugopal CHOUKINISHI ,  Xin ZHAO ,  John L. MELANSON

IPC: H04L7/033 ,  H04J3/06

CPC classification number: H04L7/033 ,  H04J3/0688

Abstract: A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.

公开(公告)号：US20230247362A1

公开(公告)日：2023-08-03

申请号：US18296266

申请日：2023-04-05

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul LESSO ,  Mark James MCCLOY-STEVENS ,  John Bruce BOWLERWELL ,  Yanto SURYONO ,  Xin ZHAO ,  Morgan Timothy PRIOR

IPC: H04R5/04 ,  H03F3/183 ,  H03G3/30 ,  H04R29/00 ,  H04S1/00 ,  H04R5/02

CPC classification number: H04R5/04 ,  H03F3/183 ,  H03G3/3005 ,  H04R29/001 ,  H04S1/007 ,  H04R5/02 ,  H03G2201/103

Abstract: This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.

公开(公告)号：US20190260365A1

公开(公告)日：2019-08-22

申请号：US16144104

申请日：2018-09-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ku HE ,  Tejasvi DAS ,  Xin ZHAO ,  Xiaofan FEI

IPC: H03K7/08 ,  H03G3/00 ,  G05F1/575

Abstract: A method may include, in a system comprising a digital PWM subsystem having a tunable digital gain, a first path coupled to an output of the digital PWM subsystem and configured to drive an open-loop driver stage, and a second path coupled to the output of the digital PWM subsystem and configured to drive a closed-loop driver stage having a tunable analog gain: selecting one of the first path and the second path for processing an input signal to generate an output signal based on one or more characteristics of the input signal, setting the digital gain to a maximum digital gain and the analog gain to a minimum analog gain when the input signal is lesser than a first threshold, setting the digital gain to a minimum digital gain and the analog gain to a maximum analog gain when the input signal is greater than a second threshold magnitude, and varying the analog gain and the digital gain when the input signal is in a range greater than the first threshold and lesser than a second threshold.