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    INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM
    16.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM 有权
    具有可编程模拟子系统的集成电路设备

    公开(公告)号：US20160065216A1

    公开(公告)日：2016-03-03

    申请号：US14668984

    申请日：2015-03-26

    Applicant: Cypress Semiconductor Corporation

    Inventor： Eashwar Thiagarajan ,  Harold M. Kutz ,  Hans Klein ,  Jaskarn Singh Johal ,  Jean-Paul Vanitegem ,  Kendall V. Castor-Perry ,  Mark E. Hastings ,  Amsby D. Richardson, JR. ,  Anasuya Pai Maroor ,  Ata Khan ,  Dennis R. Seguine ,  Bruce E. Byrkett ,  Carl Ferdinand Liepold ,  Hans Van Antwerpen

    IPC: H03K19/0175 ,  H03M1/38 ,  H03K19/003 ,  H03K19/00

    CPC classification number: H03K19/017581 ,  H03K19/0005 ,  H03K19/00346 ,  H03K19/02 ,  H03M1/1205 ,  H03M1/38

    Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

    Abstract translation: 集成电路（IC）装置可以包括多个模拟块，包括至少一个固定功能的模拟电路和至少一个可重新配置的模拟电路块，所述至少一个可重新配置的模拟电路块选自：包括多个可重新配置的放大器电路的连续时间（CT） 离散时间块，包括具有可重新配置的交换网络的放大器; 模拟多路复用器（MUX）被配置为选择性地将IC器件的多个输入/输出（I / O）中的任一个连接到模拟块，模拟MUX包括至少一个具有比其他电阻低的电阻的低噪声信号路径对 模拟MUX的信号路径; 至少一个模拟路由块可重新配置以提供任何模拟块之间的信号路径; 包括数字电路的数字部分; 以及耦合到模拟块的处理器接口。

    ULTRA-LOW POWER ADAPTIVELY RECONFIGURABLE SYSTEM
    18.
    发明申请
    ULTRA-LOW POWER ADAPTIVELY RECONFIGURABLE SYSTEM 审中-公开

    公开(公告)号：US20200083889A1

    公开(公告)日：2020-03-12

    申请号：US16369723

    申请日：2019-03-29

    Applicant: Cypress Semiconductor Corporation

    Inventor： Eashwar Thiagarajan ,  Andrew Page ,  Harold Kutz ,  Kendall Castor-Perry ,  Rajiv Singh ,  Erhan Hancioglu ,  Bert Sullam

    IPC: H03K19/173 ,  H03M1/12 ,  G06F13/28 ,  H03F3/189 ,  H03F3/72

    Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

    Configurable bus
    19.
    发明申请
    Configurable bus 审中-公开

    公开(公告)号：US20190227818A1

    公开(公告)日：2019-07-25

    申请号：US16374907

    申请日：2019-04-04

    Applicant: Cypress Semiconductor Corporation

    Inventor： Harold M. Kutz ,  Warren S. Snyder ,  Timothy John Williams ,  Eashwar Thiagarajan

    IPC: G06F9/445 ,  G06F13/42 ,  G06F13/40

    Abstract: A device includes an analog block array, a first analog bus segment coupled to the analog block array, a second analog bus segment coupled to the analog block array, and a third analog bus segment coupled to the analog block array. The device also includes a first I/O pin selectively couplable to the first analog bus segment, a second I/O pin selectively couplable to the second analog bus segment, and a third I/O pin selectively couplable to the third analog bus segment. A first switch is configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment, and a second switch is configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment. In a first mode of operation, the first and second switches are open. In a second mode of operation, the first switch is closed. In a third mode of operation, the second switch is closed.

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