公开(公告)号：US09881683B1

公开(公告)日：2018-01-30

申请号：US15496993

申请日：2017-04-25

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  Kuo-Tung Chang ,  Yoram Betser ,  Shivananda Shetty ,  Giovanni Mazzeo ,  Tio Wei Neo ,  Pawan Singh

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C7/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

摘要： Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.

公开(公告)号：US20210042245A1

公开(公告)日：2021-02-11

申请号：US16719493

申请日：2019-12-18

申请人： Cypress Semiconductor Corporation

发明人： Yoram Betser ,  Cliff Zitlaw ,  Stephan Rosner ,  Kobi Danon ,  Amir Rochman

IPC分类号： G06F13/16 ,  G06F13/42

摘要： A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

公开(公告)号：US10304545B2

公开(公告)日：2019-05-28

申请号：US15995926

申请日：2018-06-01

申请人： Cypress Semiconductor Corporation

发明人： Eduardo Maayan ,  Yoram Betser ,  Alexander Kushnarenko

IPC分类号： G11C16/28 ,  G11C8/10 ,  G11C11/56

摘要： Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.

公开(公告)号：US09773529B1

公开(公告)日：2017-09-26

申请号：US15279974

申请日：2016-09-29

申请人： Cypress Semiconductor Corporation

发明人： Kobi Danon ,  Yoram Betser ,  Alex Kushnarenko

IPC分类号： G11C16/26 ,  G11C7/06

CPC分类号： G11C7/062 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/4013

摘要： A method for operating a read command of N complementary memory cells, the method includes the steps of determining if each of the first and second memory cells of the N complementary memory cells is in a first binary state or a second binary state, generating a count value by counting a total number of the first and second memory cells that are in the first binary state, and determining if the N complementary memory cells are programmed or erased based on a result of comparing the count value to a threshold number.

公开(公告)号：US20210349839A1

公开(公告)日：2021-11-11

申请号：US17327460

申请日：2021-05-21

申请人： Cypress Semiconductor Corporation

发明人： Yoram Betser ,  Cliff Zitlaw ,  Stephan Rosner ,  Kobi Danon ,  Amir Rochman

IPC分类号： G06F13/16 ,  G06F13/42

摘要： A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

公开(公告)号：US11081194B2

公开(公告)日：2021-08-03

申请号：US16867828

申请日：2020-05-06

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  Kuo Tung Chang ,  Yoram Betser ,  Shivananda Shetty ,  Giovanni Mazzeo ,  Tio Wei Neo ,  Pawan Singh

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/10 ,  G11C7/04 ,  G11C16/24 ,  G11C16/16 ,  G11C16/26

摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

公开(公告)号：US10685724B2

公开(公告)日：2020-06-16

申请号：US16268736

申请日：2019-02-06

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  Kuo Tung Chang ,  Yoram Betser ,  Shivananda Shetty ,  Giovanni Mazzeo ,  Tio Wei Neo ,  Pawan Singh

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C7/04 ,  G11C16/24 ,  G11C16/16 ,  G11C16/26

摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

公开(公告)号：US10147734B1

公开(公告)日：2018-12-04

申请号：US15925510

申请日：2018-03-19

申请人： Cypress Semiconductor Corporation

发明人： Roni Varkony ,  Yoram Betser

IPC分类号： G11C16/12 ,  H01L27/11563 ,  G11C16/14 ,  G11C16/04

摘要： A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the third signal are received concurrently.

公开(公告)号：US20180190361A1

公开(公告)日：2018-07-05

申请号：US15877633

申请日：2018-01-23

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  Kuo-Tung Chang ,  Yoram Betser ,  Shivananda Shetty ,  Giovanni Mazzeo ,  Tio Wei Neo ,  Pawan Singh

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/30

CPC分类号： G11C16/3427 ,  G11C7/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.

公开(公告)号：US20180166141A1

公开(公告)日：2018-06-14

申请号：US15471418

申请日：2017-03-28

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  Yoram Betser ,  Kuo-Tung Chang ,  Amichai GIVANT ,  Shivananda SHETTY ,  Shenqing Fang

IPC分类号： G11C16/34 ,  G11C11/56

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344

摘要： A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.