公开(公告)号：US20050127948A1

公开(公告)日：2005-06-16

申请号：US10733537

申请日：2003-12-11

申请人： Suhwan Kim ,  Stephen Kosonocky

发明人： Suhwan Kim ,  Stephen Kosonocky

IPC分类号： G11C7/12 ,  G11C7/18 ,  H03K19/017 ,  H03K19/00

CPC分类号： H03K19/01714 ,  G11C7/12 ,  G11C7/18

摘要： This invention overcome the problems inherent in the prior art for increasing the performance of a register file that is constructed to include dual-Vt bitlines or single-Vt bitlines. The invention provides a boost of the drive signal for one of the transistors of a bitline circuit, preferably for the high voltage threshold read-selection transistor of a local bitline (LBL) circuit. The drive signal amplitude is made greater than the normal supply voltage by some increment delta V.

摘要翻译： 本发明克服了现有技术中固有的用于增加寄存器堆的性能的问题，该寄存器堆被构造为包括双V位线或单V位线。 本发明提供了对位线电路的晶体管之一的驱动信号的升压，优选地用于局部位线（LBL）电路的高电压阈值读选择晶体管。 使驱动信号幅度大于正常电源电压一些增量delta V.

公开(公告)号：US20190273439A1

公开(公告)日：2019-09-05

申请号：US16409562

申请日：2019-05-10

申请人： Nachiket Desai ,  Harish Krishnamurthy ,  Suhwan Kim

发明人： Nachiket Desai ,  Harish Krishnamurthy ,  Suhwan Kim

IPC分类号： H02M3/158 ,  H02M3/157 ,  H02M1/14 ,  G06F1/26

摘要： An apparatus is described which includes a delay-line with reasonably matched delay cells and some logic to ascertain both a correct number of DC-DC converters and interleaving angles or phase offsets. The apparatus measures an operating frequency in real-time in multiples of the individual delay cells of the delay-line. The smaller the period, the higher the load coupled to the DC-DC converters and, therefore the greater the number of DC-DC converters are needed to service the load. The period determines the load and can be used to determine the number of DC-DC converters needed and thereby accomplishing autonomous phase enabling/shedding.

公开(公告)号：US20120139584A1

公开(公告)日：2012-06-07

申请号：US13234811

申请日：2011-09-16

申请人： Hyoung-Wook Lee ,  Gun-Ok Jung ,  Suhwan Kim ,  Ah-Reum Kim ,  Rahul Singh

发明人： Hyoung-Wook Lee ,  Gun-Ok Jung ,  Suhwan Kim ,  Ah-Reum Kim ,  Rahul Singh

IPC分类号： H03K19/096

CPC分类号： H03K19/0966

摘要： A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.

摘要翻译： 多米诺逻辑电路包括第一评估单元，第二评估单元和输出单元。 第一评估单元对第一动态节点进行预充电，在时钟信号的第一阶段放电页脚节点，并且评估多个输入信号以在时钟信号的第二阶段中确定第一动态节点的逻辑电平。 第二评估单元在时钟信号的第一阶段中对第二动态节点进行预充电，并且响应于时钟信号的第二阶段中的页脚节点的逻辑电平来确定第二动态节点的逻辑电平。 输出单元提供具有根据第一动态节点的第一电压的电平和第二动态节点的第二电压的逻辑电平的输出信号。

公开(公告)号：US07714656B2

公开(公告)日：2010-05-11

申请号：US12053406

申请日：2008-03-21

申请人： Hyunjoong Lee ,  Young Sik Kim ,  Suhwan Kim

发明人： Hyunjoong Lee ,  Young Sik Kim ,  Suhwan Kim

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F1/083 ,  H03F3/45654 ,  H03F3/45659 ,  H03F2200/153 ,  H03F2203/45302 ,  H03F2203/45354 ,  H03F2203/45512 ,  H03F2203/45652 ,  H03F2203/45681

摘要： An operational amplifier including an input amplifier configured to amplify at least one differential input signal, a first common mode feedback amplifier configured to amplify a first common mode voltage, a cascode amplifier configured to cascode-amplify output signals from the input amplifier and the first common mode feedback amplifier, a first common mode voltage generator configured to generate a central voltage of the output signal from the cascode amplifier and input the central voltage to the first common mode feedback amplifier, and a frequency compensator configured to feedback the output signal of the cascode amplifier to the first common mode feedback amplifier so as to compensate a frequency of the first common mode feedback amplifier.

摘要翻译： 一种运算放大器，包括被配置为放大至少一个差分输入信号的输入放大器，被配置为放大第一共模电压的第一共模反馈放大器，被配置为对来自输入放大器和第一公共端的输出信号进行共源共放大的共源共栅放大器 模式反馈放大器，第一共模电压发生器，其被配置为产生来自所述共源共栅放大器的输出信号的中心电压并将所述中心电压输入到所述第一共模反馈放大器;以及频率补偿器，被配置为反馈所述共源共栅的输出信号 放大器到第一共模反馈放大器，以补偿第一共模反馈放大器的频率。

公开(公告)号：US20100096447A1

公开(公告)日：2010-04-22

申请号：US12530367

申请日：2008-03-07

申请人： Sunghoon Kwon ,  Youngjune Park ,  Suhwan Kim

发明人： Sunghoon Kwon ,  Youngjune Park ,  Suhwan Kim

IPC分类号： G06F17/00 ,  G06K7/10 ,  G06K19/07 ,  H04B10/00

CPC分类号： G06K19/0723 ,  G06K19/0728

摘要： The present invention relates to an optical identification tag, a reader, and a system, and more particularly, to an optical identification tag which transmits its identification information using energy input in an optical form, and an optical identification system and reader using the optical identification tag. The present invention provides an optical identification tag and an optical identification reader. The optical identification tag includes a solar cell for converting incident light into an electrical energy, a circuit for providing a transmitted electrical signal corresponding to identification information, and a light emitter for providing a transmitted optical signal corresponding to the transmitted electrical signal, and the optical identification reader provides the incident light to the optical identification tag, and receives the transmitted optical signal from the optical identification tag.

摘要翻译： 光学识别标签，读取器和系统技术领域本发明涉及光学识别标签，读取器和系统，更具体地，涉及使用光学形式的能量输入来发送其识别信息的光学识别标签，以及使用光学识别的光学识别系统和读取器 标签。 本发明提供一种光学识别标签和光学识别读取器。 光学识别标签包括用于将入射光转换为电能的太阳能电池，用于提供与识别信息相对应的透射电信号的电路，以及用于提供对应于所发射的电信号的透射光信号的光发射器， 识别读取器将入射光提供给光学识别标签，并从光学识别标签接收所发送的光信号。

公开(公告)号：US07659773B2

公开(公告)日：2010-02-09

申请号：US12022680

申请日：2008-01-30

申请人： Chang-Jun Choi ,  Suhwan Kim

发明人： Chang-Jun Choi ,  Suhwan Kim

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K17/007 ,  G06F1/26 ,  H03K17/163 ,  H03K17/22 ,  H03K17/284 ,  H03K19/0016

摘要： A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.

摘要翻译： 半导体IC包括逻辑块和控制提供给逻辑块的工作电压的电压控制电路。 电压控制电路在逻辑块的初始操作期间以逐步的方式控制工作电压的增加。

公开(公告)号：US07495596B2

公开(公告)日：2009-02-24

申请号：US11804808

申请日：2007-05-21

申请人： Suhwan Kim ,  Jong-Kwan Woo ,  Han Yang

发明人： Suhwan Kim ,  Jong-Kwan Woo ,  Han Yang

IPC分类号： H03M1/38

CPC分类号： H03M1/0617 ,  H03M1/004 ,  H03M1/1215 ,  H03M1/168 ,  H03M1/44

摘要： A signal converter such as a multi-channel pipelined signal converter includes a plurality of pipelined signal converters and a decision unit. Each of the pipelined signal converters has a respective plurality of stage cells coupled in series with switched coupling between the pipelined signal converters. The decision unit determines a respective selected path through the stage cells of the plurality of pipelined signal converters for each of a plurality of input signals during a signal path selection mode.

摘要翻译： 诸如多通道流水线信号转换器的信号转换器包括多个流水线信号转换器和决定单元。 每个流水线信号转换器具有与流水线信号转换器之间的开关耦合串联耦合的相应多个级单元。 决定单元在信号路径选择模式期间，通过多个流水线信号转换器的级单元确定多个输入信号中的每一个的相应选择路径。

公开(公告)号：US20050285628A1

公开(公告)日：2005-12-29

申请号：US10880111

申请日：2004-06-29

申请人： Suhwan Kim ,  Daniel Knebel ,  Stephen Kosonocky

发明人： Suhwan Kim ,  Daniel Knebel ,  Stephen Kosonocky

IPC分类号： H03K19/00 ,  H03K19/094

CPC分类号： H03K19/0019

摘要： A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.

摘要翻译： 提供电荷回收功率门和相应的方法，用于使用功能单元的电容性负载与电荷回收装置的寄生电容之间的电荷共享效应，以接通虚拟地面和地面之间的开关装置，电荷回收 功率门，包括第一晶体管，与第一晶体管的第一端子进行信号通信的虚拟地，与第一晶体管的第二端子进行信号通信的地，电容器，具有与第三晶体管的第三端子信号通信的第一端子 第一晶体管和与地面信号通信的第二端子，以及第二晶体管，其具有与虚拟接地信号通信的第一端子和与第一晶体管的第三端子信号通信的第二端子。

公开(公告)号：US06977519B2

公开(公告)日：2005-12-20

申请号：US10437764

申请日：2003-05-14

申请人： Azeez J. Bhavnagarwala ,  Suhwan Kim ,  Daniel R. Knebel ,  Stephen V. Kosonocky

发明人： Azeez J. Bhavnagarwala ,  Suhwan Kim ,  Daniel R. Knebel ,  Stephen V. Kosonocky

IPC分类号： H03K19/00 ,  H03K17/16

CPC分类号： H03K19/0016

摘要： A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

摘要翻译： 提供了功率门结构和相应的方法，用于控制用于多个模式的逻辑电路的接地连接，其中功率栅极结构包括NFET晶体管，与NFET晶体管信号通信的PFET晶体管，源极和漏极 分别与晶体管的漏极信号通信的接地节点和与晶体管的源极信号通信的接地轨道; 并且相应的方法包括在第一或活动模式下将逻辑电路与接地连接解耦，在第二或状态保持模式下将逻辑电路保持在接地连接以上的阈值电压处，并且切断逻辑电流之间的电流 电路和接地连接处于第三或非状态保持模式。

公开(公告)号：US6118818A

公开(公告)日：2000-09-12

申请号：US831865

申请日：1997-04-02

申请人： Cheol-Hong Min ,  Suhwan Kim ,  Seong-Jai Min ,  Seong Ok Bae

发明人： Cheol-Hong Min ,  Suhwan Kim ,  Seong-Jai Min ,  Seong Ok Bae

IPC分类号： H04N5/93 ,  G06T9/00 ,  H03M7/30 ,  H04B14/00 ,  H04N7/24 ,  H04N19/423 ,  H04N19/426 ,  H04N19/50 ,  H04B1/66 ,  H04N7/12

CPC分类号： H04N19/427 ,  H04N19/423 ,  H04N19/61

摘要： A method for decoding MPEG standard I (Intra-coded) and P (Predictive-coded) picture bit streams using a memory smaller than one video frame of data. The method includes the steps of receiving a video bit stream of an I picture and a video bit stream of a P picture in succession and storing the received video bit streams in a first memory, each of the I picture and the P picture having an up portion and a down portion, and each of the up and down portions having a top field and a bottom field; decoding the stored up portion of the I picture and storing the decoded up portion of the I picture in a first region of a second memory; decoding the stored down portion of the I picture and storing the decoded down portion of the I picture in a second region of the second memory; simultaneously decoding the stored up portion of the P picture and displaying the top fields of the up and down portions of the I picture stored in the first and second regions of the second memory and storing the up portion of the P picture in a third region of the second memory; and decoding the down portion of the P picture, waiting for display of the top fields of the up and down portions of the I picture and a predetermined number of scan lines of the bottom fields of the up and down portions I picture, and storing the decoded down portion of the P picture in the first region of the second memory.

摘要翻译： 使用小于一视频数据帧的存储器解码MPEG标准I（帧内编码）和P（预测编码）图像比特流的方法。 该方法包括以下步骤：连续接收I图像的视频比特流和P图像的视频比特流，并将所接收的视频比特流存储在第一存储器中，I图像和P图像中的每一个具有向上 部分和下部，并且每个上下部具有顶场和底场; 解码I图像的存储起始部分并将I图像的解码的上升部分存储在第二存储器的第一区域中; 对I图像的存储的下降部分进行解码并将I图像的解码的下降部分存储在第二存储器的第二区域中; 同时解码P图像的存储的上部，并显示存储在第二存储器的第一和第二区域中的I图像的上下部分的顶部场，并将P图像的上部存储在第三区域中 第二个记忆; 并且解码P图像的向下部分，等待显示I图像的上下部分的顶场以及上下部分I图像的底场的预定数量的扫描线，并存储 在第二存储器的第一区域中的P图像的解码部分。