Method for etching doped polysilicon with high selectivity to undoped polysilicon
    11.
    发明授权
    Method for etching doped polysilicon with high selectivity to undoped polysilicon 失效
    用于对未掺杂多晶硅具有高选择性蚀刻掺杂多晶硅的方法

    公开(公告)号:US06316370B1

    公开(公告)日:2001-11-13

    申请号:US09644699

    申请日:2000-08-24

    CPC classification number: H01L21/32134

    Abstract: The present invention provides an etching composition which includes a polyhydric alcohol in combination with two inorganic acids. Preferably the etching composition of the present invention is a mixture of a glycol, nitric acid and hydrofluoric acid, with propylene glycol being preferred. The etching composition of the present invention achieves a selectivity of greater than 70:1, doped material to undoped material. The present invention provides an etching formulation which has increased selectivity of doped polysilicon to undoped polysilicon and provides an efficient integrated circuit fabrication process without requiring time consuming and costly processing modifications to the etching apparatus or production apparatus.

    Abstract translation: 本发明提供一种蚀刻组合物,其包含与两种无机酸组合的多元醇。 优选地,本发明的蚀刻组合物是二醇,硝酸和氢氟酸的混合物,优选丙二醇。 本发明的蚀刻组合物实现大于70:1的掺杂材料对未掺杂材料的选择性。 本发明提供了一种蚀刻配方,其具有增加掺杂多晶硅对未掺杂多晶硅的选择性,并且提供了有效的集成电路制造工艺,而不需要对蚀刻设备或生产设备进行耗时且昂贵的处理修改。

    WAFER CLEANING WITH IMMERSED STREAM OR SPRAY NOZZLE
    12.
    发明申请
    WAFER CLEANING WITH IMMERSED STREAM OR SPRAY NOZZLE 有权
    用干燥的流动或喷雾喷嘴清洁

    公开(公告)号:US20100300491A1

    公开(公告)日:2010-12-02

    申请号:US12476139

    申请日:2009-06-01

    Inventor: Donald L. Yates

    CPC classification number: H01L21/02057 H01L21/67051 H01L21/67057

    Abstract: Several methods of removing contaminant particles from a surface of a substrate are disclosed herein. In one embodiment, the method includes directing an incompressible fluid spray onto a surface of a substrate to remove contaminant particles from the surface. In an embodiment, the surface of the substrate and the nozzle are both immersed in an incompressible fluid. The fluid can flow across the surface of the substrate to remove the contaminant particles from the area. The fluid spray can be positioned normal to the substrate surface, or can be positioned at an angle relative to the substrate surface.

    Abstract translation: 本文公开了从衬底的表面去除污染物颗粒的几种方法。 在一个实施例中,该方法包括将不可压缩的流体喷雾引导到基底的表面上以从表面去除污染物颗粒。 在一个实施例中,基板和喷嘴的表面都浸没在不可压缩流体中。 流体可以流过基板的表面以从该区域去除污染物颗粒。 流体喷雾可以垂直于基底表面定位,或者可以相对于基底表面成一定角度定位。

    LOCALIZED MASKING FOR SEMICONDUCTOR STRUCTURE DEVELOPMENT
    13.
    发明申请
    LOCALIZED MASKING FOR SEMICONDUCTOR STRUCTURE DEVELOPMENT 有权
    用于半导体结构开发的本地化掩模

    公开(公告)号:US20090102018A1

    公开(公告)日:2009-04-23

    申请号:US12276152

    申请日:2008-11-21

    Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

    Abstract translation: 用于集成电路的容器结构及其制造方法,而不使用机械平面化(例如化学机械平面化(CMP)),从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

    Compositions for Dissolution of Low-K Dielectric Films, and Methods of Use
    14.
    发明申请
    Compositions for Dissolution of Low-K Dielectric Films, and Methods of Use 审中-公开
    低K电介质膜溶出的组合物及其使用方法

    公开(公告)号:US20080283796A1

    公开(公告)日:2008-11-20

    申请号:US12168475

    申请日:2008-07-07

    Inventor: Donald L. Yates

    Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

    Abstract translation: 提供了用于清洁半导体晶片的表面的改进的组合物和方法。 该组合物可用于选择性地除去低k介电材料,例如二氧化硅,覆盖低k电介质层的光致抗蚀剂层,或从晶片表面两层。 根据本发明配制组合物以从晶片的表面提供低k电介质和/或光致抗蚀剂的期望的去除速率。 通过改变氟离子成分以及氟离子成分和酸,成分和控制pH的量,可以配制组合物以实现期望的低k电介质去除速率,其范围从慢和约在约 每分钟50至约1000埃,以每分钟大约1000埃的速度相对快速地除去低k电介质材料。 组合物也可以配制成选择性地除去光致抗蚀剂层,使底层的低k电介质层基本上完整无缺。

    Layered magnetic structures having improved surface planarity for bit material deposition
    15.
    发明授权
    Layered magnetic structures having improved surface planarity for bit material deposition 有权
    具有改进的钻头材料沉积的表面平面度的分层磁结构

    公开(公告)号:US07402879B2

    公开(公告)日:2008-07-22

    申请号:US11134321

    申请日:2005-05-23

    CPC classification number: H01L27/222 G11C11/15 H01L21/7684

    Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

    Abstract translation: 本发明提供了一种制造存储单元的一部分的方法,该方法包括提供一沟槽中的第一导体,其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化,形成材料层 在绝缘层和第一导体的平坦的上表面上方,并且使材料层的上部平坦化,同时在绝缘层和第一导体上完整地保留材料层的下部。

    Semiconductor processing patterning methods
    16.
    发明授权
    Semiconductor processing patterning methods 失效
    半导体加工图案化方法

    公开(公告)号:US07384727B2

    公开(公告)日:2008-06-10

    申请号:US10609311

    申请日:2003-06-26

    Inventor: Donald L. Yates

    CPC classification number: H01L21/0274 G03F7/095 H01L21/3085

    Abstract: The invention includes semiconductor processing patterning methods and semiconductor constructions. A semiconductor processing patterning method includes forming a second composition resist layer over a different first composition resist layer. Overlapping portions of the first and second composition resist layers are exposed to actinic energy effective to change solubility of the exposed portions versus the unexposed portions of each of the first and second composition resist layers in a developer solution. The first and second composition resist layers are developed with the developer solution under conditions effective to remove the exposed portions of the first composition resist layer at a faster rate than removing the exposed portions of the second composition resist layer. Additional aspects and implementations are contemplated.

    Abstract translation: 本发明包括半导体处理图案化方法和半导体结构。 半导体处理图案化方法包括在不同的第一组合物抗蚀剂层上形成第二组合物抗蚀剂层。 第一和第二组合物抗蚀剂层的重叠部分暴露于有效地改变曝光部分相对于显影剂溶液中第一和第二组合物抗蚀剂层中的每一个的未曝光部分的溶解度的光化能。 第一和第二组合物抗蚀剂层与显影剂溶液一起显影,条件是有效地以比除去第二组合物抗蚀剂层的暴露部分更快的速度除去第一组合物抗蚀剂层的曝光部分。 考虑另外的方面和实现。

    Device having improved surface planarity prior to MRAM bit material deposition
    17.
    发明授权
    Device having improved surface planarity prior to MRAM bit material deposition 有权
    在MRAM钻头材料沉积之前具有改进的表面平面度的装置

    公开(公告)号:US07375388B2

    公开(公告)日:2008-05-20

    申请号:US10734201

    申请日:2003-12-15

    CPC classification number: H01L27/222 G11C11/15 H01L21/7684

    Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

    Abstract translation: 本发明提供了一种制造存储单元的一部分的方法,该方法包括提供一沟槽中的第一导体,其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化,形成材料层 在绝缘层和第一导体的平坦的上表面上方,并且使材料层的上部平坦化,同时在绝缘层和第一导体上完整地保留材料层的下部。

    Acid blend for removing etch residue
    18.
    发明授权
    Acid blend for removing etch residue 有权
    用于去除蚀刻残留物的酸性共混物

    公开(公告)号:US07261835B2

    公开(公告)日:2007-08-28

    申请号:US10338845

    申请日:2003-01-09

    Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.

    Abstract translation: 从半导体衬底干法蚀刻工艺后残留的有机金属和有机硅酸盐残渣的方法。 将基底暴露于磷酸,氢氟酸和羧酸(例如乙酸)的调理溶液中,其除去剩余的干蚀刻残留物,同时最小化从所需底物特征中去除材料。 调理溶液的大致比例通常为80至95%的乙酸,1至15%的磷酸和0.01至5.0%的氢氟酸。

    Compositions for removal of processing byproducts and method for using same

    公开(公告)号:US07018937B2

    公开(公告)日:2006-03-28

    申请号:US10231416

    申请日:2002-08-29

    Inventor: Donald L. Yates

    Abstract: A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine compound. The semi-aqueous composition includes glacial acetic acid and one or more components including a fluoride compound and a pyridine compound. The composition can be used in removing processing byproducts from substrate assembly, including MRAM devices, that include at least a metal containing region and processing byproducts, where removing the processing byproducts includes exposing the substrate assembly to the composition for a time effective to remove at least a portion of the processing byproducts.

    Compositions for dissolution of low-K dielectric films, and methods of use
    20.
    发明授权
    Compositions for dissolution of low-K dielectric films, and methods of use 有权
    用于溶解低K电介质膜的组合物及其使用方法

    公开(公告)号:US06762132B1

    公开(公告)日:2004-07-13

    申请号:US09652991

    申请日:2000-08-31

    Inventor: Donald L. Yates

    Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

    Abstract translation: 提供了用于清洁半导体晶片的表面的改进的组合物和方法。 该组合物可用于选择性地除去低k介电材料,例如二氧化硅,覆盖低k电介质层的光致抗蚀剂层,或从晶片表面两层。 根据本发明配制组合物以从晶片的表面提供低k电介质和/或光致抗蚀剂的期望的去除速率。 通过改变氟离子成分以及氟离子成分和酸,成分和控制pH的量,可以配制组合物以实现期望的低k电介质去除速率,其范围从慢和约在约 每分钟50至约1000埃,以每分钟大约1000埃的速度相对快速地除去低k电介质材料。 组合物也可以配制成选择性地除去光致抗蚀剂层,使底层的低k电介质层基本上完整无缺。

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